Testable Design And Testing For The OR-Coincidence Logic System

The continuous decrease of feature size leads to large increase in the integration and complexity of integrated circuits and test has been a great challenge for VLSI design. To ease the task of test and reduce the test cost and time the design for testing (DFT) method in logic design is an important subject in VLSI design. As an important complementarity for AND-EXOR logic, OR-Coincidence logic has shown some attractive advantages over the traditional Boolean logic based on AND-OR-NOT in certain applications, for examples in implementation of arithmetic-logic functions and linear or nearly linear functions. The expression of OR-Coincidence logic requires fewer number of sum terms in many applications and can save chip area. Additionally, OR-Coincidence logic has great advantage of easy testability that is of potential value for DFT. This dissertation systematically discusses DFT and test method based on OR-Coincidence logic system for detecting stuck-at faults and further explores the testability of AND-EXOR and OR-Coincidence logic by the form of the latter.There exits four forms for the expression of OR-Coincidence logic: PPOC (positive polarity OR-Coincidence expansion), FPOC (fixed polarity OR-Coincidence expansion), GOC (generalized OR-Coincidence expansion), CPOS (Coincidence products-of-sum) and the latter form includes the former. The Exclusive-NOR circuits for implementing coincidence logic in general has two structures—cascade and tree, the latter suitable for the situation when the input variable-number is large and the circuits speed need to be high. First the easily testable networks based on OR-Coincidence logic are researched and the easily testable networks means that the number, regularity and degree of generation difficulty of its test vectors are of obvious advantages over the traditional circuit networks. The easily testable networks of PPOC with Exclusive-NOR cascade for detecting single or multiple stuck-at-fault — PPOC-CS(M) (C denotes Exclusive-NOR cascade, S and M denote single and multiple stuck-at-fault) are proposed. Two kinds of typical Exclusive-NOR trees and their testable structures are proposed and generating methods of the two kinds of minimal testable Exclusive-NOR trees are given. Based on this the easily testable networks ofPPOC with Exclusive-NOR tree for detecting single or multiple stuck-at-fault— PPOC-TC(M) (T denotes Exclusive-NOR tree) are proposed. Based on easily testable PPOC networks, the corresponding easily testable FPOC, GOC and CPOS networks are proposed. DFT methods is proposed for general polarity networks composed of FPOC and easily testable GOC and CPOS networks when complementary inputs are provided. Compared with testing of traditional circuits, test sets of all the proposed easily testable networks for detecting single stuck-at-fault are universal and the cardinal numbers are very small. The test sets of easily testable networks for detecting multiple stuck-at-faults are also comparatively regulative and can be generated easily. The needed control and observation points and other test logic by the easily testable networks for detecting single or multiple stuck-at-fault are very or comparatively few, so a good balance between the load of test logic and testability is reached.Finally Boolean difference method in the form of OR-Coincidence algebra and testing of combinatorial networks of OR-Coincidence type universal logic gates using this method are proposed. The concept of inverse Boolean difference is introduced. Its calculation properties and method and test pattern generating functions based on it are given. The Boolean difference method in the form of OR-Coincidence provided concise and rigorous mathematic tools with evident significations for application of Boolean difference method in OR-Coincidence type combinatorial networks. The discussion on testing shows that OR-Coincidence type universal logic gates have strong logic functions and can be used to simplify networks structure, so the chances for faults to occur and test load are reduced. Using this kind of gate in digital design is beneficial to testing.