Boolean Process And Waveform Simulator

Owing to progresses in manufacture technology and EDA tools, transistor density and operation frequency of an integrated circuit have been increased rapidly. Consequently, challenges include how to represent logic function and timing behavior of a circuit under a high operation frequency with an analytical approach, how to rapidly and accurately simulate circuits with large scale by EDA tools, and how to test those more and more complicated circuits. This thesis focuses on those questions. Creative contributions of the thesis are mainly shown in the following.1. A Boolean process based waveform simulator.The proposed simulator is a numerical waveform simulator with high speed and adequate accuracy, which can simultaneously reflect logic function and timing behavior of a circuit. There are several special features, including (1) it can use different gate-level delay models depending on speed and accuracy requirements of simulation, (2) it can simulate feedback free circuits, and circuits with feedback as well, (3) it can assign different delays to different gates in a circuit, and (4) it can delete unpractical glitches generated by signal propagation in simulation. Some parameters of basic gates have been measured by SPICE simulation, so that various gate delay models can be built for the waveform simulator to meet different requirements of speed and accuracy of simulations. Experimental results show that the waveform simulator can speed up a simulation several ten thousands times by using fixed delay model comparing to SPICE. On the basis of analyzing factors that contribute to gate delays differently, this thesis proposes a multi-factor delay model, which can offer a more realistic simulation, according to simulation experiments.2. A deterministic BIST approach using LFSR-ROM scheme.The test pattern generator of the proposed BIST approach consists of a LFSR and a ROM. The LFSR generates a great number of random test patterns to detect most ease-to-detect faults, while the ROM generates a few deterministic test patterns...