Research On Multi-Fault Test Generation Algorithms And Design For Testability Of Digital Integrated Circuits

Microelectronic technique is one of the most rapidly developing techniquesin technological field at present. With the advancement of its design andproduction process, integrated circuits (ICs) are becoming more and morecomplex and larger and larger in scale, making the test for the chips increasinglydifficult. In the meantime, higher requirements for circuits test have been putforward, thus the research on test generation algorithms are drived forward. Asthe traditional test generation algorithms no longer meet the requirements, thekey points in ICs testing research mainly focus on new and more effective testgeneration algorithms and design for testability of Digital Integrated Circuits.In this dissertation, the multi-fault test generation algorithms and design fortestability of combinational circuits have been studied for the purpose ofimproving faults coverage, reducing the test generation time, the generation andapplication of test patterns. The main contents of this thesis are as follows:Based on the research on two-valued neural networks model, three-valuedneural networks model for combinational circuits has been established andapplied successfully to test generation algorithms for combinational circuits. Byconstructing the constraint networks of circuits to be tested, using geneticalgorithm and fitness function proposed in this paper, through programming, theminimum of the energy function to correspond with the constraint network can begotten. By means of simulation, the test patterns of faults can be obtained forbenchmark circuits. Further, the comparative results of three-valued and two-valuedmodels have been presented. If digital circuits are represented by three-valuedneural networks model, the search space can be reduced and many unnecessaryassignments can be avoided. Therefore, the method can reduce test time andimprove test efficiency. The test generation algorithms based on Boolean difference forcombinational circuits has been studied. Considering that there are a lot ofexclusive OR operations in the Boolean difference, we proposed single fault ordouble faults test generation simplified method with constraint conditions. In thisway, multi-fault can be equated into single fault or double faults forcombinational circuits, test patterns can be obtained only by solving the identityand constraint conditions without exclusive OR operations.In accordance with EST algorithm, a kind of test generation algorithm hasbeen studied based on search state dominance for combinational circuits. Takingthe advantage of the dominance relation of the E-frontier (evaluation frontier),we can prove through some examples that this algorithm can prune the searchspace more effectively than the EST algorithm. The calculated test patterns candetect the given faults with the help of the simulation.Since generating test patterns are not needed in the course of Syndrometesting, Syndrome of circuits has been thoroughly studied. As the logicalexpression is needed to be given for the traditional Syndrome test, it is difficultto test for the VLSI. In this dissertation, first order and second order Syndrometestable new conditions have been derived, and the high-order test Syndrometestable condition can be obtained therefrom. By making use of it, we can fulfillthe judgment of high-order Syndrome directly with no need of giving the logicalexpression. In addition, it can be ensured that Syndrome of circuits would betestable.Design for testability based on Reed-Muller pattern for combinational circuitshas been studied. In consideration of the problem that test patterns generation ofcombinational circuits needs much resource, we have made a research on thecombinational circuits based on Reed-Muller pattern. The circuit structure ormodule designed in this way may be tested by general test patterns set. It can notonly detect single-fault easily, but also define ihe fault location. Besides, thedouble-fault and multi-fault can also be detected by this method.In order to decrease the test patterns, it is necessary to analyze the faults incircuits and find out the relationships among all kinds of faults. This paperpresents a kind of method that combines parallel faults simulation with Booleansimplified method for determining the minimum test patterns set. By using the results of parallel faults simulation, the corresponding relationship between faultpoints and test patterns can be determined, also, the minimum test patterns setcan be gotten based on Boolean simplified method.