Research On Test Generation And Fault Diagnosis For Analog Circuits

The problem of test generation and fault diagnosis for analog circuits raised a great deal of interest recently. The testing in the analog systems is more difficult because of the continuous values of the signals in the time and frequency domains, the tolerance problem, the limited test points and the response dependence on topological structure and so on. This paper is focus on the analog test generation and fault diagnosis, including a test generation algorithm based on Support Vector Machine(SVM), a multi-frequency test generation algorithm based on an improved fault model, feature selection and fault location based on Component Connection Model(CCM). The contributions of this paper are as follows:(1)Most of the current test generation algorithms are only fit to enumerable faults. These algorithms are invalidated when occuring many unenumerable parametric faults. To address this problem, this paper proposes a test generation algorithm based on SVM. Many engineers have been working on SVM in testing. However, most of their works focused on fault diagnosis, and none focused on test generation. The test generation algorithm based on SVM in this paper can avoid enumerating many parametric faults and building transfer functions of the systems, and deal with the linear classification in mixed sample space.(2)In order to solve the signal redundancy and the unsteady state of learning result, this paper improves the test generation algorithm based on SVM in three points.①When the bandwidth of the analog systems is much smaller than the sampling frequency, sample space contains redundant data. The redundancy will waste the needless computational load, and result in redundancy of the test signals. To address this problem, this paper proposes a k-nearest neighbors method and a sample mean method to compress sample space.②In the test generation algorithm based on SVM, every circuit instance, which may be normal or faulty instance of the analog system, needs a unique test signal. When occurring many unenumerable parametric faults, the analog system needs a large number of test signals. This can influence testing speed strongly. This paper proposes a method based on Euclidean distance to compress the test signal set.③The training sets are randomly generated, so they can lead to the unsteady state of the efficiency in the test generation. To address this problem, this paper proposes a method combining multi-training sets to judge the test results.(3)Current multi-frequency test generation algorithms use a single value to represent a fault in the fault model. But the single values cannot substitute for the actual faults that may occur, because the possible faulty values vary over a continuous range. To address this problem, this paper proposes a multi-frequency test generation algorithm based on an improved fault model. To ehance the precision of this test generation algorithm, this paper uses genetic algorithm to optimize the pivotal parameter.(4)When the analog systems occur small parametric faults because of environmental stress, the features of these faults aren’t obvious, and these faults may be mixed in the noise. It’s very difficult to detect these faults. To address this problem, this paper proposes two different feature selection methods, which include a conditional-probability method and a conditional-entropy method. The theory analysis and the experiments show that the conditional-entropy method can achieve high detection rate and low detection time.(5)CCM is a classical method to describe electronic systems, for building fault location equations. It uses matrixes to represent component characteristics and connection relationship, then the fault location can be perform by matrix operation, and convenient to operate by computers. However, in the nonlinear analog systems, the computational load may increase rapidly with the system scale and the precision of the nonlinear model. To address this problem, this paper improves the fault location based on CCM in two points.①Decrease the dimension of the fault location equations by deleting unsensitivity components.②This paper proposes a hierarchical method for the fault location in large-scale systems. This method constructs a hierarchical fault model, and restricts the dimension of the connection matrix to the number of the components in the lowest module. It can decrease the scale of the fault location equation efficiently.(6)In the fault location based on CCM, current sensitivity analysis algorithms didn’t refer to the effect from choice of trees’set. This paper proposes a sensitivity analysis algorithm to choose optimal trees’set and test points based on CCM.