Research On Architecture Design For DSPs-Based Media Processing System-on-chip

The architecture of media processing system on chip (SoC) could be classified into two kinds based on its implementation method: ASIC's and programmable ones. The programmable one is the trend of the industry with the high-speed technical development of semiconductor, microprocessor and media processing algorithms. Media SoC based on DSPs is a research hotspot in VLSI field. The research in this paper focuses on the several key issues of programmable media processing SoC: DSP architecture and micro-arhictecture, SoC architecture and task scheduling.In the last few years, Department of Information Science and Electronic Engineering in Zhejiang University developed the first member for MD32 series' DSP: MediaDSP3201.In this paper, to improve the media processing capability compared to MediaDSP3201, MediaDSP3202 will be designed. MediaDSP3202 inherits the pipeline structure's characteristic of MediaDSP3201. As a fact, media application algorithms are always the driving force of DSP architecture. In MediaDSP3202, according to characteristic of the media application algorithms, the EMS instruction set which supports 128 bit SIMD operations in width will be designed; Several single-clock bit-operation instructions will be designed for VLD decoding according to processor pipeline; To improve the implementation performance for IDCT and MC, some special SIMD instructions also will be designed.A kind of distributed bypassing unit strategy will be introduced considering MD32's micro-architecture optimization. The proposed strategy adopts an effective mechanism to avoid unnecessary pipeline stall. A bypassing circuit chain model is used to realize the proposed strategy in MD32 series' DSP. Considering circuit delay, a circuit optimization method is used to avoid pipeline stage delay to be increased. So the overall performance will be improved.After a comparison beteen two implementation schemes, a progromable media processing SoC based on two processor cores will be designed named MediaSOC3221A which can be used as audio and video decoding system for MPEG-like standard.The task scheduling for media SoC based DSPs includes processor task scheduling and bus task scheduling, and processor scheduling can further more be classified into global task scheduling and local task cheduling. Software/hardware co-design method will be used for global processor task scheduling which is a static method. Futher more optimization for local processor task scheduling also will be proposed. Considering characteristic of media processing task, a dynamic priority-based method will be designed for bus task scheduling with multiple request sources. The proposed method also can be used in other media processing SoC.