Research On Architecture Design For Programmable Media Processing System-On-Chip

Media processing SoC is a research hotpot of VLSI. The research in this paper focuses on the several key issues of programmable media processing SoC, such as architecture, task scheduling, bus arbitrating, and memory subsystem etc.The architecture of media processing SoC could be failed into two classes based on its implementation method: ASIC's and programmable ones. And the later is the trend in the industry with the high-speed technical development of semiconductor and microprocessor. Media enhanced extension is introduced based on the algorithms of media processing according to the architecture of MD32. After the discussion of the two architectures, the author proposes a hardware structure of programmable media processing SoC with dual-core, and implements the design of digital A/V decoding SoC, compatible with MPEG series. Also, how to embed MD32 into this media system organically is also discussed, and the reuse of MD32 core makes the system work smoothly, promoting the flexibility and programmability.Media processing SoC is a complicated real-time system, within which so many tasks are running on the limited hardware resources. The scheduling of software/hardware is one of key problems of the real-time media processing system designing. As a case, the digital A/V decoding SoC with dual-core is discussed. Using software/hardware co-design method, the tasks are mapped into 2 classes: one is relative to master processor (RISC32), the other is relative to media processor (MD32). As to tasks on the master processor, the corresponding task-scheduling method is proposed through analyzing the characteristics of program and data streams of software. For the tasks relative to MD32, the structure is optimized to improve the utilization of calculation resources of the media processor core. To achieve real-time video decoding, a data-driven control strategy is proposed.To solve the bus design and data transfer, an enhanced bus interface structure is adopted to transfer bulk data. Based on this structure, an optimized bus arbitration method is studied combining the highest fixed priority with dynamic ones, which is testified to meet the requirement of hard real-time task and system performance both. As the memory subsystem is one of the key issues, a hierachical memory structure is designed, through which, system can be "prefetch" the media data, exploiting the parallelism of calculation and transportation in temperal domain, promoting the system performance. Multi-channel 2-dimension DMA controller is also designed to archieve further performance of the hierachical memory structure.