Research On Techniques Of Embedded Streaming Media Processor Architecture

Embeded streaming media processing is the embedded application field to research how to transfer real-time and reliable streaming media information based on low-bandwidth wireless networks and restricted computing and memory resources on mobile terminals. Developing ESMP (Embedded Streaming Media Processor) is the primary approach to implement this target and has become an important research interest in industry and academe.ESMP integrates the functions of streaming media processing, including signal collection, conversion, encoding, storage, decoding and input/output, into a single SoC (System-On-a-Chip) chip. ESMP has many advantages, such as fast, high integration and low power, and can find applications in many fields including military scout, mobile communication, wireless surveillance and video meeting. Although some advanced streaming media international standards and SoC design technologies have been carried out, the implementation of ESMP on a single SoC chip faces many challenges coming from short design cycle time, high complexity, strong flexibility, strict design constraints and so on.In this paper, we combine the two design ideas of dedicated architectures and instruction set extensions based on an international popular ESMP architecture frame. To achive the best tradeoff among real-time performance, flexibility and low power dissipation, in this method, the algorithms with high computing complexity are implemented by dedicated architectures, and the new algorithms with low real-time requirements are accelerated and updated in time by instruction set extensions. This paper puts the most efforts on the fundamental and kernal techniques including the dedicated architectures of some key algorithms in MPEG-4 streaming media system, an enhanced streaming media instruction set, and Hi-PBD (Hierachical Platform-Bashed SoC Design) method, resulting in the following achievements:1. We propose a new DCT/IDCT architecture based on Wallace trees. This DCT/IDCT architecture distributes the multiply/accumulate with fixed coefficients into additions for partial products at first, then decreases the number of additions by sharing subexpression, and accumulates all partial products to get the transform result based on optimized Wallace trees at last. The new architecture does not need ROM (Read Only Memory) and multipliers any more, but utilizes low cost adders, shifts and 4-2 compressors to implement multiplication dense DCT/IDCT algorithm. It develops the furthest common structures between DCT and IDCT and shares and reuses immediate data and hardware resources adequately. All above features enable its application for low power and real-time processing. This architecture can achieve 300Mpixels/sec throughput at the frequency of 300MHz with cost of 10,605 gates and 1,024 bits transform memory. The experiment result shows its superiority over existing architectures.2. We propose a flexible, efficient and configurable motion estimation architecture. The core of this motion estimation architecture is a motion estimation engine CPAME (Configurable Parallel Array Motion-estimation Engine), which supports the latest efficient BMAs (Block...