On The Design Of Multi-Processor System-On-Chip For Media Processing

Rapid improvement of chip design techniques and the deep-submicron technology havedriven the embedded system design into System-On-Chip (SoC) era. Meanwhile, more and morecomplex algorithms for media processing require higher performance of SoC. The programmablemulti-processor-based SoC is receiving more and more attention for its high performance andflexibility for real-time media processing.The author attended the development of a media SoC, namely MediaSoC3221A, and amulti-mode processor, namely RISC3202, which were both designed by the SoC R&D Group ofZhejiang University. The research work introduced in this thesis mainly concerns the design ofmedia multi-processor SoC (MP-SoC), including data transporting mechanism, multi-modeprocessor, audio/video synchronization and task scheduling.Media processing for large data streams requires not only high the data calculating ability, butalso the efficient data transporting mechanism. Direct memory access (DMA) technology totransport data is widely adopted into the designs. But more complex MP-SoC design brings thenew challenge to data transporting. The author analyzed the storage characteristics of media dataand described the task-chain based two-dimension DMA mechanism for media data transporting.The centralized DMA controller was designed for the bus-on-chip based MP-SoC. Meanwhile thedistributed DMA controller was designed for the network-on-chip based media MP-SoC. Amethod was proposed for the front design of asynchronous circuits. The experiments resultsindicated that the task-chain based two-dimension could effectively improve system performance.The processor is the key unit in embedded media MP-SoC. Based on 32 bit single-issueprocessor RISC3201, a multi-mode processor RISC3202 was designed to satisfy the requirementsof different applications. RISC3202 can operate with three modes: dual-issue mode, dual-coremode and dual-thread mode. During the design, the IP reuse methodology was adopted intomixing the micro-architecture of multiple modes. The pipeline hazards were analyzed and solvingmeasures proposed. A finite state machine (FSM) based centralized control scheme was proposedto supervise the pipeline activities. The thread switch with low cost was implemented. Comparingwith RISC3201, the performance of RISC3202 improved 70～80%, while the gate cost of pipelineincreased 105%.Base on the development of heterogeneous MP-SoC for audio/video decoding, a mechanismwith feed-back was implemented to synchronize audio and video. With system feed-back, thesystem clock frequency and the audio play-back frequency were adjusted in real time. Theplayback of video frame was adjusted according to synchronization. To reduce performance lossresulted from bus task conflicts in media processing, a scheme to optimize bus scheduling forMP-SoC was proposed. This scheme combined bus task property modification with bus taskpriority adjustment to optimize bus scheduling. Experiments showed that processor performanceloss in MediaSoC3221A was reduced from 4.7% to 0.1% during real-time MPEG decoding.