Method Of Validation And Test Of DSP And Platform Design

With the development of integrated circuit technology and to circuits scale, digital signal processor becomes more and more powerful, based on versatile signal processing technology. However, such progress challenges designers to propose more effective verification methods. How to design digital signal processor with good testability, to generate programs for verification and to create suitable verification platforms appear as key issues of digital signal processor design.The author takes charge of verification and validation for a 16-bit fixed-point DSP, named MD16. In order to achive good testability, verification coverage and faster speed, this paper proposed severel methods for the following problems: design for test of signal digital processors, generation of verification programs and development of hardware/software co-design platform. Therefore, the time-to-market of digital signal processors is shortened.The main contents and innovative points included in this paper are as follow: To reduce scan time and delay time of critical path in the method based on chain, a Embedded-In Circuit Emulator (EICM) was proposed. Based on IEEE 1149.1 protocol, instructions and scan chain were introduced. With test access port (TAP) module exchanging serial input with parallel output, register files and random access memory (RAM) on chip were read or written in parallelism. Experiment results EICM cut down scan time and the bad effect on critical path brought by scan chain. The time on testing chip can be reduced greatly, and the development process of digital signal processor becomes faster. To satisfy different requirment of validation and testing for digital signal processor, a functional validation and testing method is proposed. Using the method of Software/Hardware Co-validation, the speed of validation and testing accelerated. Testing coverage rate of instruction was highly improved by testing program of instruction based-on model of instruction. Using pipelined control based validation model, data hazard between instructions was detected. Experiments show that instruction coverage achieves 100 percent, and also code coverage of DSP is satisfied with the specification ? To meet different requirement of co-simulation, co-verification and testing for digital signal processor (DSP), A reusable software-hardware co-verification and test platform for DSP is proposed. Using reconfigurable IP module and bus-based method, Reconfigurable and reusable hardware platform was realized. Using embedded in-circuit module (EICM), real-time verification and test was implemented. Using hierarchical design method, reconfigurable software was implemented. The experiments result shows that the software-hardware verification and test platform can simulate instruction set as well as simulate application program. Media processor poses new challenges for design-for-test (DFT), with development of designtechnology of Media processor and appearance of heterogeneous Media system-on-chip. In this paper, the design way of hierarchy architecture is proposed to solve the program of control for multi-TAP and flexibility of test, the impact on top-TAP controller states is decreased and stability is increased by the definition of SELECTED and UNSELECTED instruction when test-mechanism IP modules are tested, The test flexibility is increased and test time is decreased obviously by adding instruction of DEBUG and OSELECTED and bus-based access method, when no-test-mechanism IP modules are tested. The result indicated that the revised part of TAP controller increased 5% compare to the standard TAP, completely compatible with IEEE 1149.1 protocol as well. MD16 chip has been successfully tested. The results show that the chip can operate at162MHz@l .8V, with the power consumption of 1 .lmW/MHz.