Research On The Design Of PLC Processor Based On State Machine

With the rapid development of PLC's applications,to the processor requirements of PLC also will continue to improve.PLCs' need processors to be as inexpensive as commercial processors,and to be increasingly data processing like DSP processors,especially with real-time processor performance on industrial applications.In this thesis,the development status,development direction,working mode and working demand of the existing PLC and its processors are studied and analyzed.On this basis,a real-time and efficient processor to PLC application is designed PLC processor based on state machine.After research,the author puts forward the concept of high efficiency processor and state cluster in this thesis,regarding the state cluster as the innovation of this thesis.Efficient processor concept is to minimize the code as much as possible to complete the data processing.The detailed description is MDPS(Millions of Data Per Second)and DIR(Data Instructions Ratio).State cluster concept is through the main state machine from the slave state machine to cluster state to realize the complex and repetitive specific data processing operations(section SFR of 8051 single-chip microcomputer is CPU under the control of a configurable state cluster).Avoiding bus repeat instruction fetch caused by the occupation,in order to obtain a higher efficiency than the RISC data processing,higher than the flexibility of DSP,throughing the array addition and search list the examples are explained in detail the specific.Following design of PLC processor based on state machine design has completed in this thesis: processor architecture design(operator integration for array addition and linked list search),design of processor system(design of program counter,design of instruction fetch operation,design of instruction set,design of code and design of special function register).Description language programming using Verilog HDL hardware master,state machine,state cluster,cluster state memory,processor state machine etc..The Verilog implementation of the state machine instruction includes: the realization of the general instruction,the realization of the state group instruction,the realization of the data block operation and the realization of the special function.Using Modelsim and SE software,combined with FPGA doing the logic function simulation validation for the PLC processor which based on state machine instructions of general state cluster,timer,interrupt,array addition and search list,the simulation results proved the feasibility of PLC processor based on state machine.