| The increasing use of Digitial Signal Processors (DSPs) is a clear trend in the telecommunications,multimedia,and consumer electronics industries. With the fast development of the technology of System On Chip (SOC),more and more embedded systems are implemented in IP cores. This commonly leads to a hardware DSP system partitioned into an embedded DSP core. So it is very critical to design the system and architecture of an embedded DSP core.This thesis discusses the issues related to the design of embedded multiprocessor systems,with the focus on DSP-based systems. This thesis from the development of DSPs view divides the development process of DSPs into four main stages and summarizes the characteristics of DSPs. And aiming at the late DSPs,the single and multi issue architecture DSPs are designed and implemented. In this thesis,a new design method is presented and a method of resolution of VLIW DSP shortcomings is also put forward.Two points should be noticed in designing embedded DSP processors:1. The DSP has a customizable architecture that has a native support for adjustment of a wide range of core parameters and it also allows straightforward extension of the instruction set. These customization capabilities can be exploited to characterize the processor ISA to match the exact needs of a given application.2. Most DSP cores are supported with a compiler and a simulator,available via the processor vendor. However,in the case of fixed-point DSP processors,it is well known that the code quality produced by these compilers is often insufficient. In most cases these tools are based on standard software compiler techniques,which are not well suited for the peculiar architecture of DSP processors. As a result,current day's design teams using DSP cores are forced to spend a large amount of time in handwriting of machine code (usually assembly code). This situation has some obvious economical drawbacks. Programming DSP's at such a low level of abstraction leads to a low designer's productivity. Moreover,it results in massive amounts of legacy code that cannot easily be transferred to new processors. This situation is clearly undesirable,in an era where the lifetime of a processor is becoming increasingly short and architectural innovation has become key to successful products. So a system design method combined tightly with the compilation should be applied in present embedded DSP system designs.Under the two points mentioned above,we designed a 16 bits DSP core-MD16. This core has a data-width of 16 bits and an instruction-width of 24 bits with all the instructions completed within a five-stage pipeline. This DSP core is realized in a 0.35um CMOS technology and can work at above 80MHz. In order to inprove the performance of MD16,one method is transforming the architecture to the multi issue architecture.So a VLIW DSP core is set up. But VLIW architecture characters its wide instruction bandwidth. Aiming at solving this disadvantage,a VLIW model is built and a novel method of instruction compression is presented. This method is made up of two ways of instruction compression,the horizontal way and the vertical way,with features of easy,fast implementation,and simple hardware implementations. These two ways are demonstrated by being applied to the two datapaths' DSP architecture. Also,the hardware decompression module is designed in 0.25u technology and its simulation results are described. The simulation results show the hardware overhead is decreased. |
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