Research On The Design Of Low-Voltage Low-Power NMOS And ECL Circuits

This dissertation proceed from the principle of that reducing supply voltage of circuits is the most efficient way to decrease the dissipation of circuits, and first, discuss the difficult of conventional nMOS and ECL circuits performing at low-voltage in standard technology which do not reduce the threshold voltage of the transistor, and point out this is due to the structure of cascade switches, so, when supply voltage is reduced to a certain magnitude, the circuit will not perform correctly. Then, the dissertation proposed the idea that adopting the structure of parallel switches to design low voltage nMOS and ECL circuits, and according to the theory of switch-signal. several methods for converting cascade switches to parallel switches which are suitable for design nMOS and ECL circuits are proposed. Based on this, several binary and ternary nMOS circuits and ECL circuits with parallel switches are designed at switch-level. The simulation and measured result shows that, the designed circuits using parallel switches technique have correct logic functions, and the binary nMOS circuits can perform correctly with 1 .OV supply voltage, the ternary nMOS circuits can perform correctly with 3.3V supply voltage , and the binary and ternary ECL circuits can perform correctly with the supply voltage which magnitude are lower than 1 .2V and 2.OV respectively; the all designed circuits have low power dissipation. In addition, the ECL circuits designed with parallel switches have smaller propagation delay than the conventional counterparts with cascade switches.