Design On Strained MOSFET Based Stress Management For CESL Using Trench Structure

Strained Silicon is the most promising method to enhance the performance of MOSFET and increase the integration density of sub-micron devices, which can suppress the short channel effect effectively and improve switching speed and driving ability of the device. The advantage of uniaxial strain technology over biaxial strain is that the carrier mobility enhancement is larger and the device threshold shift is not obvious. Silicon nitride cap layer technology is one of the most important uniaxial strain technologies, but there are still many problems for its application in CMOS process: 1) Compressive and tensile CESLs need to be fabricated on the same wafer, the relative process is complicated. 2) When the size of the device channel is further reduced, the boundaries of N-channel and P-channel become difficult to distinguish. This paper presents a deep trench based structure for modulating stress in the channel of the device introduced by stain CESL(Contact Etch Stop Layer), its modulation mechanism is studied and process is designed.First, the composition and formation mechanism of silicon nitride film stress is discussed. A dynamic cooling of the thermal stress simulation is used, comparing to conventional static thermodynamic simulation the result of this method is more realistic, which takes the temperature dependent material properties into account. Depending on the mechanism of Silicon Nitride intrinsic stress, the diffusion principle of H atoms in the film is used to establish the stress model of a silicon / silicon nitride system. This model is consistent with experimental data.Secondly, based on the basic principle solid state physics that protrusive structure can gain enlarged stress in local area, a deep trench structure is used to expand the scope of stress and change the type of stress. The simulation results show that a deep trench structure without oxide inside has the opposite stress effect with the traditional STI process when stressed by Silicon Nitride capping layer. The simulation also shows that the process of trench structure based MOS is compatible with standard CMOS process. The electrical simulation result is consistent with stress data, where the driving ability of trench based NMOS is improved by 13.5% compared to controlled device.Finally, in order to achieve the accurate measurement of MOS device channel region stress. Based on deep trench MOS process, we put forward a method to add electrode in channel width direction and measure the resistance change of the channel width direction in order to calculate the strain along gate length direction. This method that can measure the stress in a tiny area in MOS channel without destroying the original channel stress builds up the relationship between electrical characteristic and stress by silicon piezoresistive coefficient. Then we design the process of deep trench based MOS strained by Silicon Nitride capping layer which is compatible with strained Silicon process.