Reliability Study Of Silicon Nanocrystal Memories

With the scaling of microelectronics technology, the conventional flash memories based on the polysilicon floating gate have encountered serious technical challenges due to the tradeoff between the oxide thickness and long time retention. Silicon nanocrystals (Si-NCs) nonvolatile memory is a promising candidate for the next generation application due to its potential advantage in scalability, low cost and full compatibility with CMOS process. In automobile and embedded application, Si-NCs memory devices have attracted extensive attention from academy and industry with the merits in high retention. However, the special geometric structure of Si-NCs memory results in the complicated affecting factors for the endurance characteristics. To meet the zero-fault stringent safety requirement for automobile application, Si-NCs memory devices still face challenges from endurance degradation currently.In this work, endurance degradation of Si-NCs memory devices under Fowler-Nordheim program and erase (P/E) cycling is investigated.Firstly, some technical methods for the device performance characterization and reliability studying have been introduced. As the basic characteristic, the capacitance-voltage (CV) and current-voltage (Id-Vg) curves are often used in the characterization of the memory window, program/erase speed, endurance, and data retention and so on. The quasi static CV (QSCV)-high frequency CV (HFCV) measure, the Sub-threshold Swing (SS) extracting, the charge pumping (CP) mearsure and the mid-gap voltage calculation are often used to analyze the device mechanism deeply. And the characteristic of endurance, retention and disturb test are the basic parameters of the reliability.Then the methods of SS, CP current and mid-gap voltage shift have been used to analyze the endurance degradation of Si-NC memory devices under FN P/E cycling by varying program and erase voltages. It is found that the generation of interface traps dominates the threshold voltage (Vth) degradation, and the high erase voltage causes severe Vth, degradation by generating more trapped oxide and interface traps charges. After that, the interface degradation of Si-NCs memory devices under FN P/E cycling has been characterized by CV and CP tests. It is found that the mean density of the acceptor-type interface traps increases more rapidly with increasing the cycling number and shows a higher density than the donor-type ones. The dominant mechanism of the interface degradation was the generation of acceptor-type interface traps.In order to have more information of interface traps and find the root cause of the interface traps generation, the energy spectra of cycling-induced interface traps of Si-NCs memory devices are extracted by the high-low CV method. Four clear broad peaks are observed in the cycled devices which different from the common Pb-type "double peak" in the fresh device. With respect to the valend band edge, their positions are centered at about0.3(â… ),0.47(â…¡),0.7(â…¢) and0.85(â…£) eV, respectively. The densities of peak III and IV are higher than those of peak I and â…¡. Peak I and â…£ are identified from the amphoteric Pbo centers. And the charge pumping test shows that peak III is more active than peak â…¡. Based on the energy position and electrical activity, peak II may be from Pb1centers. The understanding of the degradation mechanisms will be helpful to further optimize the process flow and to improve the endurance performance of Si-NCs memory.Finally, a novel drain-junction assisted hot electron programming scheme has been proposed for optimizing the reliability of Si-NCs memory devices. Two electron injection paths are responsible for our proposed scheme and more electrons have chance to inject into Si-NCs. Our experiment results show that the new method increase the memory window nearly â…£ and fast the program speed almost1000times than the conventional CHE injection. Meanwhile, retention and endurance characteristics also have been improved. This new scheme shows to be more promising for Si-NCs memory application.