| Nanocrystal (NC) based nonvolatile memories have been studied extensively owing to their discrete-trap storage behaviors for largely immunizing the local oxide defects, and are regarded as a promising candidate for future non-volatile memory (NVM) application. Metallic-NC memory devices can have higher program/erase (P/E) efficiency, lower operating voltage, larger capacities, and longer retention times than their semiconductor counterparts, because it is difficult to control the trap levels and density to ensure device reliability. Besides, the device fabrication process is not complex and more controllable, and can be formed by various techniques.In this paper, a transient electrical model, taking into account the impacts of Si surface potential, thermal excitation and Coulomb blockade effect, were proposed, and then the earrier (electron and hole) charging and discharging processes in a metal NC memory were simulated. Research results indicated that, for a tunnel oxide of2.27nm is thick enough to guarantee ten years retention time, and the program and erase time can reach4.35and21.4μs at±10V applied voltage. Moreover, the flat band voltage shift△VFB and the charge density Qnc of the NC-embedded MOS capacitor are greatly dependent on the start sweep gate voltage (VG) and the sweep rate dV/dt. The memory window increases steadily from0.86to8.30V with the increase of the start applied gate voltage from±2to±6V. As the sweep rate decreases from10to0.0001V/s, the memory window increases from0.11to5.77V, and△VFB and Qnc will reach a saturation state on the assumption that the sweep rate is slow enough. Also, the flat band voltage shift△VFB rapidly achieve to saturation value as the pulse time increased at various operation modes (i.e. program and erase operation), suggesting large carrier injection efficiency for both electrons and holes in such a short time. We also adopt magnetron sputtering and rapid thermal annealing (RTA) to prepare nickel NC-based metal-oxide-semiconductor (MOS) capacitors, which were fabricated at various annealing temperature for30s with the same initial film thickness. The optimum temperature to obtain the best surface morphology and maximum dot density is about700℃, the nickel NC uniformity and disperse, mean diameter and NC density is16.7nm and1.28×10-11cm-2, respectively. The charge storage effect was investigated by high frequency capacitance-voltage (C-V) measurement. As the annealing temperature increase, the memory window increases first and then decreases, the largest charge storage effect is achieved at700℃. A window (～2.02V) is observed for the device at±8V sweep range, and the device has the least leakage current (1×10-9A/cm2) and good insulation property.MOS capacitors embedded with self-assembly NCs were fabricated by a simple method based on magnetron sputtering under different substrate temperature (250/275/300/325℃). The charging/discharging characteristics and charge storage effect were investigated by high frequency C-V measurement. The memory windows first increase to maximum value, and then decrease with the increase of growth temperature. A largest memory window (2.78V) was achieved at300℃substrate temperature. It should be noticed that, in terms of the same sweep voltage, the memory effects of the MOS devices which are prepared with different processes (RTA and direct deposit self-assembly) are very different, the latter (300℃) is much larger than the former (600℃), and lower growth temperature so as to economize device fabrication thermal power consumption. Moreover, the flat-band voltage shifts under different operations voltages and pulse times were also investigated, a large flat-band shift was observed as the operation voltage increases up to±10V, indicating that an occurrence of strong carrier (electrons and holes) injecting. Furthermore,△VFB shifts rapidly close to saturation value as the accumulated time up to5.0s, and increases tiny while prolonging pulse time. |
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