Fabrication And Simulation Of InP Nanocrystal Floating Gate Memory

With the development of semiconductor technology and the decrease of device feature size,the traditional floating gate memory is confronted with the problem of increasing device leakage.Nanocrystals,the discrete charge storage structure,are used as charge storage layer.Nanocrystal floating gate memory has been widely studied for its low working voltage,high erasing speed and compatibility with CMOS process.This paper will combine theoretical simulation and experimental preparation to study InP nanocrystalline floating gate memory.In the theory,according to the charge transport and tunneling mechanism of nanocrystal floating gate memory,the retention characteristic model of single-layer nanocrystal floating gate memory is established by combining the relationship between electron direct tunneling current and threshold voltage deviation.Firstly,the retention characteristic curves of Si,Ge and InP nanocrystals as storage layers were simulated respectively to verify the performance advantages of InP nanocrystalline used in simulation and experiment.Density,coverage and other factors of InP nanocrystals which affect the retention characteristics are simulated.The simulated results show that compared with the traditional Si and Ge nanocrystals,InP can effectively improve the charge retention characteristics of devices due to its narrow bandgap and larger barrier height.At the same time,higher nanocrystal coverage can effectively improve the retention characteristics of the device.However,due to the mutual limitation between size and density,InP nanocrystals with appropriate size and density were prepared in subsequent experiments under the premise of ensuring nanocrystalline coverage.In the experiment:?1?memory capacitors with Al/HfO₂/InP NCs/ZrO₂/Si structure and InP as storage medium were fabricated.The effects of 1.5min,2min and 2.5min post-annealing of the deposition on InP nanocrystals with thickness of 2nm,3nm and 4nm were studied.Experimental results show that both 1.5min and 2min post-deposition annealing of 2nm InP storage layer and 2min annealing of 3nm InP can form nanocrystals with appropriate size and density.Under the programming/erasing voltage of±8V,the memory windows of 4.5V,4.7V and 4.9V are respectively obtained,and the charge loss ratio is 18.2%,22.4%and 20.2%.?2?Memory capacitors of Al/HfO₂/InP NCs/ZnO/ZrO₂/Si structures with ZnO and ZrO₂ as tunneling layers of double barriers were prepared.InP nanocrystals were prepared by 2nm thick InP film after 2min post-deposition annealing.The experiment shows that the InP nanocrystal memory capacitor with double barrier tunneling layer structure can obtain a 4.85V storage window under the programming/erasing voltage of±8V.The 100ns programming/erasing operation can generate a 3.3V memory window with a high charging speed and a 29.7% charge loss ratio.