| With the continuous development of integrated circuit technology,the feature size of the memory cell decreases and the integration of memory chip increases at the same time.The traditional poly-silicon flash is gradually faced with the reliability problems.In order to guarantee the data reliability,the poly-silicon flash memory still possesses a tunneling oxide layer with 7 nm in thickness.It's hard to meet the requirements of low bias,low power consumption,and high-speed memory in daily life.Therefore,the nanocrystal floating gate memory based on discrete charge storage emerges at a historic moment.It is using laterally isolated nanocrystals instead of poly-silicon which based on continuous charge storage.The charge stored within the nanocrystals can't transfer between each other and will never leak out completely through one sneak-path generated in the tunneling oxide layer.As a result,an ultra-thin tunneling oxide layer can be used to remarkably decrease the operating voltage and raise up the operating speed,while with no reliability degradation occurred.Moreover,the fabrication technology of silicon nanocrystals(nc-Si)is mature,which is compatible with the traditional Si based CMOS integrated circuit technology.Thus the nc-Si floating gate memory has the wide application prospect.Based on the excellent electrical characteristics of nc-Si memory,my research work is combined with the major national research projects of our group,which is investigation of semiconductor silicon quantum dots memory and device physics.I am as the key research member of the project group,successfully complete the research task of the project under the cooperation of the united laboratories of SMIC and the test group of Shanghai Institute of Microsystem and Information Technology,which is exceeding the expected research target and is rated as outstanding project by the Ministry of Science and Technology.The main research contents and innovation results of this paper are listed as follows.1.Based on the research results of the major national research projects,the key process technology is applied into the 0.13 ?m standard CMOS process line in SMIC.We have fabricated the ultra-thin SiO2 tunneling layer of 3.2?3.5 nm,and the uniform nc-Si floating gate layer with the average size of 12 nm,high surface density of 1.8×1011cm-2,the Standard Deviatio(STDEV)of 1.5 nm,and the monodispersity of 12.5%,as well as SiNx control layer of 26 nm.The dangling bonds on the surface of nc-Si can be passivated by using nitridation treatment.As a result,the interface states between nc-Si with SiNx control layer and ultra-thin SiO2 tunneling layer can be effectively reduced.The SiNx cover layer acted as potential barrier can suppress the releasing of stored carriers among the nc-Si and leakage from nc-Si to channel through the tunneling oxide layer.2.We have carried on the key technology design,layout design and device structure design of nc-Si floating gate nonvolatile memory cell based on 0.13 ?m process node,and successfully fabricated the nc-Si floating gate MOSFET memory cell on 0.13 ?m standard CMOS process line in SMIC.The cell gets an "Off" current is 100 fA.,the On/Off ratio is up to 107 and the subthreshold swing is lower than 0.13V/decade.After programmed and erased by ±7V/10?s pulse,respectively,the cell can get a memory window of about 1 V,which is large enough for a typical sense amplifier to defect.Besides,the cell shows a very good immunity to the disturbance of low bias and good data retention characteristics.More importantly,the pulsed endurance testing demonstrates performance up to 107 P/E cycles,which is much higher than the traditional flash memory cell(104).Generally,our nc-Si floating gate memory exhibits very wonderful characteristics such as low operating voltage,low power consuming,high speed,long endurance and so on.3.The influence of the memory cell scaling down on the electrical characteristics of the device was studied.It is found that the memory window is independent on the memory cell gate area,which is mainly determined by the size and area density of nc-Si.The P/E speed characteristics are independent on the gate length and width.The erase speed is faster than the program speed.The data retention characteristics are also independent on the memory cell gate area.This provides a certain reference for the fabrication of the memory cell with smaller feature size in future.The nc-Si floating gate MOSFET memory cells with excellent electrical characteristics were further integrated to fabricate 8Kb NOR function memory chip.We have studied the disturb phenomena among the memory cells in array caused by the integration of memory cells.As the results of 4×4 NOR function memory array show,the read,write and erase operation voltage offset for the memory array were selected and optimized,which can effectively overcome the disturb problem among the memory cells in array.This provides a reliable basis for the write/erase measurement and demonstration of 8Kb NOR function memory chip.4.We have successfully fabricated the first piece 8Kb NOR function nc-Si floating gate memory chip with the peripheral circuit on 8 inch wafer on the 0.13 ?m standard CMOS process line in SMIC of china.We used the DIP 48 black ceramic cartridge for chip packaging to fabricate the prototype device.Meanwhile,we designed a PCB test card for the function demonstration of memory chip,as well as taken on the single bit tests and full write/full erase tests for the prototype device.Moreover,we have successfully written a string of English letters into the prototype device,then read from the prototype device and been displayed on the LCD display of the PCB test card.Compared the English letters of written with that of read,it is found that they are completely consistent.This indicates that the nc-Si floating gate memory prototype device indeed realize the memory function of text.It provides a reliable reference for the fabrication of memory cell with smaller feature size and memory chip with larger capacity. |
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