Optimization Of Material And Processing For Interface Passivation Layer Of Ge MOS Devices With High-k Gate Dielectric

Traditional Silicon CMOS device has been increasingly approach to its physical limits after decades of development,resulting in difficulty in the futher scaling and low power consumption.Ge shows greate potential in preparation of P-MOSFET due to its highest hole mobility in currently known semiconductor.The recent development of high-k gate dielectrics makes Ge channel become one of the most promising candidates.However,the formation of native oxide GeO_x?x<2?on the surface of Ge substrate,which degrades the device performance,is the key problem in preventing the development of Ge MOSFETs.Therefore,in this thesis,investigation on optimization of material and processing for interface passivation layer of Ge MOS devices with stacked high-k gate dielectric are carried out.Firstly,Ge MOS capacitor with stacked gate dielectric of HfTiON/TaON is faricated,and the preparation processes are investigated.By investigating the influences of three post-deposition annealing?PDA?temperatures?400°C,500°C,600°C?and two atmospheres?NH₃,N₂?of plasma treatment on interfacial and electrical characteristics of the devices,the appropriate PDA temperature?500°C?and atmosphere?NH₃?of plasma treatment is determined.Experimental results show that the sample annealed at 500°C and performed plasma treatment with NH₃ exihibits low interface-state density(D_it=9.54×10¹¹eV^-1cm^-2)and small gate leakage current density(J_g=9.49×10^-5 A/cm² at V_g=1 V)have been obtained.Based on the above experimental investagation,NH₃-plasma treatment is performed at different steps during fabrication of the stacked gate dielectric,i.e.the surface of Ge,TaON and HfTiON.The effects of NH₃-plasma treatment at different interfaces on interfacial and electrical properties of Ge MOS devices are investigated.Experimental results show that better interface quality and electrical properties with lower interface-state density of4.79×10¹¹eV^-1cm^-2 and smaller gate leakage current density of 3.43×10^-5A/cm² at V_g=1 V have been achieved for the sample with NH₃-plasma treatment directly on Ge surface before TaON deposition.In order to further reduce gate leakage current density and improve the reliability of the device,Ge MOS capacitors using Y-incorporated TaON as interface passivation layer?IPL?are fabricated to study the effect of Y incorporating on interfacial and electrical properties and the content of Y incorporation of TaYON IPL is optimized.Experimental results show that an appropriate doping of Y content in TaON interlayer can effectively improve the interface quality and electrical performance for Ge MOS devices.The sample with a Y/Y+Ta atomic ratio of 27.6%exhibits the best interface quality and electrical properties in this thesis with lowest interface-state density of 2.83×10¹¹eV^-1cm^-2 and smalest gate leakage current density of 2.57×10^-5A/cm² at V_g=1 V have been achieved.