Simulation, Analysis And Logic Design Of Single-electron Transistor

One by one, single electron can tunnel across single electron transistor(SET) fromsource to drain port. Compared with traditional CMOS circuits, SETs can potentiallydeliver high device density and power efficiency at good speed. Recently, SET can befabricated with CMOS on a same wafer, which can be used to design many useful logicsto extend the application region of SET/CMOS hybrid circuits. Therefore, based on thecurrent development of SET, we analyze several new characteristics of SET, then proposea novel logic design method to utilize Coulomb Oscillation of SET, and design severalreconfigurable logic gates and multiple value logic gates based on SET/MOSFET hybridcells. The main innovations in this work are summerized as follow:1. An analytical model of SET conductance is proposed. By the model, several char-acteristics of SET conductance are analyzed. With period of T(vds), Drain-sourcecondutctanceG_ds ofSETdecreaseswithincreasingofdrain-sourcevoltageV_ds. G_dsconverges to the inherent value Const, which is determined by device parameters.Compared with non-blockade region, temperature affect conductance much moreremarkably. Also, resistances and capacitances of junctions affect the drain-sourceconductance of SET.2. A method is proposed which can be used to systematically analyze the NDR effectof the SET and some organic layers. The SET will exhibit NDR if the region la-bel increases with V_ds. With increasing |dV_gs/dV_ds|, the NDR becomes clearer and1/PVR increases correspondingly. The NDR effect of a SET (e.g. 1/PVR) can betuned by|dV_gs/dV_ds|, C_g/C_s, C_g/C_d, and the second gate voltage of a double-gateSET.ThreeNDCcellswereanalyzedindetailwithourmethodandtheresultsshowthat the method is novel and provides efficient analysis of NDR for SETs and someorganic layers.3. A logic design method based on tunable coulomb oscillation is proposed. We in-vestigate the tunable characteristics of coulomb oscillation about SET, and proposea novel method to design SET logic gates, which is based on the tunable periodicfunction and definition of THmnW gate. Simulation results show that the method can be simply and flexibly used to design many more complicate THmnW logicgates, which are very useful for the Very Large Scale Integration of SET devices.4. Reconfigurable logic gates are designed based on SET/MOSFET hybrid circuits.Reconfigurable SET-inverter logic gate is designed and validated firstly. Next, ac-cording to current development of SET fabricating process, two types of reconfig-urable logic gates based on SET/MOSFET hybrid circuits are designed. Comparedwith traditional MOSFET circuits, the cells can realise reconfigurable functionswith high performance and at lower cost of area and power, which is very usefulfor the design of the very large scale integration based on SET circuits.5. AnimprovedMCmethodtosimulatetheSETdevicewith1-Dimensionmultipleis-lands is proposed. Compared with other methods, the method can simulate the SETdevice with high speed and excellent accurateness and good convergence. Nor-mally, the improved MC method, is suitable for the ASIC design of SET deviceswith high speed and accurateness.6. Critical characteristics of The drain current of 1-D multi-island SET periodic in-creasesanddecreaseswiththegatevoltageV_gsi inperiodofe/C_gi. Eachgatevoltage,thermo-electrons and background charges can all affect the coulomb characteristicof multi-island SET. So although SETs with multi-islands is much more attractivethan single-island SETs, there are still many more effects unpredictable needed toavoid.