Study Of Single-electron Transistor At Room Temperature

Compared with classic CMOS logic circuit, SET(single electron transistor) circuit benefit from low power and high density. State of art manufacturing technology can produce SET which works under normal temperature, and the SET processing technology is compatible with CMOS technology, these improvements lead hybrid SET-CMOS to practical. Following the technology trends of SET, under normal temperature environment, this thesis analysis the new feature of SET, proposed Pseudo-NMOS-like logic circuit and reconfigurable logic. The major innovation is as follows:1. This paper improved analytical model for conductance of single-electron transistor(SET). The model is set up according to the relation of conductance,drain-source current and voltage of SET, and conductance is partial derivatives of IDSon VDS, not derives from physical mechanism of conductance of SET. Based on this model, thesis verified the characteristics of conductance to gate-source voltage and that of conductance to drain-source voltage, which is consistent with the I-V characteristics such as Coulomb oscillation, Coulomb blockade and Coulomb staircase of SET completely. Especially, this by analyzing and proving, This model is suitable for SET from super-low temperature to room temperature(0K < T ≤ 300K), moreover, negative differential conductance of SET is validated and elementarily analyzed using this model.2. Proposed SET analyzing model based on energy quantization at normal temperature, and verified this model using the size of SET. From the Orthodox Theory, derivate and calculate the critical size of the SET,6.9nm for memory device and 1.7 nm for logic device. derivate and calculate the critical size of SET occurring energy quantization:2.3nm,then verify and analysis these three critical sizes. Through comparison, we get the conclusion for the design of SET under normal temperature: logic device should take energy quantization into consideration and memory device should not. Considering the side-effect of energy quantization,thesis proposed solution to avoid energy quantization based on the achievement get from the manufacturing of normal temperature SET: hybrid SETMOS is good choice.3. We propose pseudo-NMOS-like logic architecture based on hybrid SETMOS,which is similar to the pseudo-NMOS logic based on pure MOSFET, and can work normally at room temperature with high performance. The pseudoNMOS-like logic gate only uses 2 MOSFETs and n SETs instead of 2n MOSFETs in the compensatory MOSFET logic or n+2 MOSFETs in the pseudoNMOS logic. We investigate the pseudo-NMOS-like inverter, NAND2 gate,NAND3 gate, NOR2 gate, NOR3 gate and 3-input hybrid PDN gate, and simulate the important characteristics of them in terms of voltage swing, area,delay, power dissipation and driving capability, respectively. Compared with pure MOSFET logic, the pseudo-NMOS-like logic proposed in this paper can implement the same function at much lower costs of area and power; compared with pure SET logic, it can achieve higher voltage swing and driving capability. In a word, the pseudo-NMOS-like logic based on the hybrid SETMOS is very useful for the very large scale integration, and will be perhaps the acceptable substitute for the compensatory MOSFET logic along with continuously shrinking the minimum physical dimensions of the device.4. A novel reconfigurable pseudo-NMOS-like logic architecture based on hybrid SETMOS is proposed. It is shown that the hybrid SETMOS logic is much like to the pseudo-NMOS logic not only in form but also in function it performs,therefore, the hybrid SETMOS logic is named pseudo-NMOS-like logic. Based on pseudo-NMOS-like logic and the reconfigurable inverter/buffer cell, we propose a reconfigurable pseudo-NMOS-like logic architecture, A representative3-input logic element on the basis of this architecture is illustrated at room temperature, and its power, delay and voltage swing are evaluated. This architecture can be extended to any n-input reconfigurable pseudo-NMOSlike logic, and each logic element can implement up to 2n kinds of functions with different configurations by only using 1 PMOS, 1 NMOS and n SETs,which significantly reduces area and power consumption. The reconfigurable pseudo-NMOS-like architecture can be applied to applications such as functional memory systems, FPGAs, etc.5. Proposed reconfigurable single SET multi input logic. We analyzed the pseudoNMOS-like logic from mechanism, discovered that the reconfigurable feature of SET determines the reconfigurable feature of this logic. Based on thismechanism, we proposed another reconfigurable logic based on SETMOS: reconfigurable single SET multi input logic. In this hybrid SETMOS logic, the structure is fixed, which is composite of serial connected PMOS, NMOS and SET, the function of the circuit can be changed through adding capacitance input in the gate terminal of SET. Since this has the reconfigurable feature,we name it reconfigurable single SET multi input logic. Based on the structure of reconfigurable single SET multi input logic, we designed reconfigurable NAND/NOR logic circuit. For arbitrary logic function, reconfigurable single SET multi input logic can save area through using 1 PMOS, 1 NMOS and 1SET.