Research On Techniques Of Soft Error Estimation For Nanoscale Integrated Circuits

The continuous development of IC manufacturing technology brings people and industry lots of benefits, such as widely improved chip integration and performance, and unceasingly shrunk device area and supply voltage. However, the aggressive technology scaling also brings IC designers and manufacturers more reliability challenges, in which, soft error is a serious one, especially in nanoscale technology. Meanwhile, factors like negative bias temperature instability (NBTI) and propagation induced pulse broadening (PIPB) induced transient pulse broadening, and multi-cycle aware pulses overlap also further aggravate circuit failures. Previous works show not only that the failure ratio caused by soft errors in combinational logic has already been comparable to that in storage elements, but also that approximately 20% soft error rate (SER) and circuit delay increment are detected when a circuit endures 10-years NBTI.In order to accurately estimate the sensitivity of ICs to soft errors, and further provide guidelines for selective radiation hardening, the techniques of soft error estimation for nanoscale ICs by input-vector and probability based methods are presented. This dissertation details SER evaluation flow considering NBTI and PIPB induced transient pulse broadening, and multi-cycle aware pulses overlap factors. The main contributions of the dissertation are as follows:(1) Re-convergence-aware SER Estimation for Nanoscale ICs. As to re-convergence considered SER estimation issue, an input-vector based SER estimation technique is introduced in this dissertation. Sensitized paths and delay were firstly computed by the proposed re-convergence aware sensitized path searching algorithm after gate-level simulation and fault injection. Further, by propagating the simulated pulses through the gate cells on re-convergence paths, electrical and timing masking was evaluated by pulse-masking models. As a result, SER of target circuits was effectively calculated by the proposed SER estimation technique. Experimental results show that the proposed technique gains a higher accuracy on account of considering re-convergence.(2) Aging-aware SER Estimation for Nanoscale CMOS Circuits. As to pulse broadening issue, an aging-aware SER estimation technique for nanoscale CMOS circuits is proposed. Width of SET pulses generated in a gate cell was broadened by first-hit SET pulse broadening model, after mapping the PMOS threshold voltages calculated by NBTI models into predictive technology model (PTM) cards, broadening ratio of pulses propagating through logic gate cells was measured by aging-aware simulation program with integrated circuit emphasis (SPICE) tool. As a result, SER induced by the broadened pulses latched by storage elements was computed. Experimental results show that the proposed technique accurately computes SET induced SER in ICs’ life time, and provides guidelines for instructing selective hardening of ICs in early design stages.(3) A Latching-Window Masking Model considering Overlapped Transient Pulses in Multi-Cycle. As to pulses overlap and overlapped pulse induced soft error in multi-cycle, a novel latching-window masking model considering overlapped transient pulses in multi-cycle for advanced CMOS technology is proposed. Sensitized paths and delay were accurately calculated firstly by the proposed re-convergence aware sensitized path searching algorithm. Further, on re-convergence paths, pulses were overlapped by the proposed pulses overlap calculation technique. Finally, failure rates were computed by the proposed model. Experimental results show that the proposed technique improves 7.5% SER accuracy on average by comparing with the multi-cycle pulse-overlap not considered approach within acceptable simulation time overhead.(4) Fault-Probability based SER Estimation for Nanoscale ICs. As to incomplete input-vector space and slower SER estimation speed for input vector based methods, a fault-probability based SER estimation technique for nanoscale ICs is proposed. Signal probability of each gate was computed firstly by means of a circuit simulator, then fault was simulated by reversing output signal probability of a gate, and data paths from the fault simulated gate to latches were retrieved by path searching algorithm. Further, the injected particles were simulated by SET pulses with different widths, and then error probability of circuits was estimated by pulse masking models. As a result, SER of circuits was computed by the proposed SER estimation approach. Experimental results show that the proposed approach is approximately 200X faster than the input-vector based method and haves a similar accuracy of SER estimation for ISCAS’89 circuits.