Design And Research On A-IGZO-based TFT

Thin film transistor(TFT) is an important part of the active organic light emitting diodes and liquid crystal display. In recent years, the excellent properties of transparent metal oxide semiconductors, such as the amorphous IGZO, has attracted and excited the market. They are becoming the best selection of the next generation of liquid crystal display, taking the place of silicon to provide better performance. This thesis will study the a-IGZO-based TFT on the following points.The defect states between the active layer and dielectric layer of TFT is an important parameter to control the device performance. Therefore, this thesis firstly analyze of the effects of band tail state, deep level detects and interface charge of TFT performance. The results show that the defects of band tail affect the on-sate characteristics of devices; the defects of deep level effect the sub-threshold states region of the devices; when interface charges increase from Qf=1.0E11 to Qf=4.0E12, the mode of the devices will change from enhancement mode to depletion mode. So, in the actual preparation, it is necessary to optimize the process conditions and reduce the defect density between the active layer and the medium interface.The dielectric constant of the dielectric layer is also important parameters affecting the performance of the devices. Different dielectric constants of the dielectric layer are considered, and mainly in the high dielectric constant material, to study the properties of a-IGZO TFT. And in the study, for the influence of the interface between materials to the characteristics, a stacked SiO2/high-K dielectric structure is designed as gate dielectric layer; thickness of the stacked structure has been optimized to achieve better device performance. Besides, the thickness of the active layer also has impaction on device performance. So it is optimized to get much better performance of the devices. In the study, the device channel length is 30 um, and the optimized thickness parameters of SiO2/HfO2 stacked layer are 30/50 nm to be the gate dielectric layer, the active layer thickness is optimized to be 120 nm. And the optimized device performance is as follow: current off ration of 108, threshold voltage of 2.62 V, the field effect mobility was 13.5cm2/vs.Based on the above study, a dual-gate a-IGZO TFT is design and studied in different bias modes. By contrasting the short-circuit connection mode enables the device best performance the bottom-contact mode and the top-contact mode. In compare with the single-gate TFT, when the channel length is reduced to 4 um, the threshold voltage shift for the single device is large, it may be due to the short channel effect. While for the double-gate devices, the threshold voltage floats only within a certain range and suppresses the short channel effect. At last, the process of double-gate TFT is simulated by Athena software.