Research On Multiprocessor System-on-Chip Based On Reconfigurable Technology

Traditional signal processor cannot satisfy the high performance requirement with the limited manufacturing process, which prompts the development of MPSoC. Compared with traditional multi-core system, the processor units of MPSoC are integrated in one chip, which decreases the communication delay among processor units as well as decreases system energy consumption. Therefore, MPSoC is the trend of future computer development. However, there are also some bottleneck problems, whose core is how to guarantee and increase the parallel efficient of MPSoC. In accordance with the existing problems, this paper did deep research in communication mechanism, parallelism-design model, routing algorithm, topology architecture and other critical areas in MPSoC. The main research results are following:(1) Proposed a double-model-fusion communication mechanism. A double-model-fusion communication mechanism, which adopts different transmission channel to transmit data according to the character of interactive data between processors, is proposed in order to solve the inefficient communication. Based on data’s character, double-model-fusion mechanism divides the exchange data into control information and data information, transmitted in separate channels. Based on double-model-fusion communication mechanism, replication-division-parallel transmission is proposed to decrease the processors’schedule consumption. Double-model-fusion communication mechanism is realized on reconfigurable platform, which uses particle filter algorithm as example. The experimental results show that the double-model-fusion communication mechanism can increase the data exchange ability and enhance the overall system’s parallel efficiency.(2) Proposed a multiple-level-parallel model. According to the problem in high scalability and high performance in multi-media embedded application, we designed a multiple-level system, which divides the design into three levels:the system level, transaction level and statement level. According to the requirement, the task was decomposed from system level to statement level, use different parallel granularities in different levels, achieve parallel maximum in different granularity levels. Based on this model, this paper presents an AVI video compression and real-time storage system. The experimental results show that good real-time performance can be realized by adopting multiple-level-parallel model.(3) Proposed a NoC-oriented obstruction-perception-routing-based algorithm. In order to solve the routing delay problem and route node link obstruction problem, we proposed local-obstruction-perception-based TF-XY routing algorithm. This routing algorithm adopts global dimension-order and local adaptive rules, probe-feedback strategy is used by the neighboring routing nodes to perceive the surrounding blockage state of current node. The experimental results show that this algorithm has higher data throughput compared with similar topology. At last, we implemented FPGA-based Mesh topology and routing node based on TF-XY routing algorithm. Under the premise of the shortest routing path, compared with XY Dimension order algorithm, TF-XY routing algorithm can bypass blockage area efficiently.(4) Proposed a Half-Mesh-based NoC topology. Existing topology only considers task and data transmission, but always neglects the fact that task arrangement and protocol are finished on key point. In order to shorten the routing path length between key point and ordinary point, we proposed halve-thought-based Half-Mesh topology. Through adding row-column head node and row-column center-node long connecting line, this topology shortens the path length between control node and other nodes. This topology enhances the data communication ability between control node and ordinary node and reduces routing delay. Based on Half-Mesh topology and TF-XY routing algorithm, we proposed HTF-XY region divided routing algorithm, dividing the NoC network. The span area routing adopts the long connecting line in priority, within the area we adopt TF-XY routing algorithm. At last, we implemented 7x7 FPGA-based Half-Mesh topology and the corresponding routing algorithm. The experimental results show that in different dimensions, path lengths between head node and ordinary nodes under Half-Mesh topology are shorter than Mesh topology. What’s more, HTF-XY routing algorithm has made the routing delay shorter and routing diversity better.