Design And Implementation Of A Hierarchy-Bus Communication Architecture Of Multiprocessor System-on-Chip

Integrating multiple processors on the single chip to improve the SoC's (System-on-Chip) performance has been becoming a trend. And the leading challenge is the communication architecture. Traditional design of SoC was based on the single-layer bus, but with the increment of IPs (Intellectual Property), the efficiency of communication between them is becoming a bottleneck and, worsens the whole system. Instead of using the single layer bus in traditional SoC, hierarchy bus based architecture is proposed in our MPSoC (Multiprocessor System-on-Chip) Platform. Local traffic communicates through a local bus and, the global pattern transfers through the second layer bus. A Bus bridge is hired to connect with each other.This dissertation is supported by the following projects: the project of 'Basic Research of Networks-on-Chip Architecture and the Design Methodology' supported by the National Natural Science Foundation of China (NSFC,№:60576034); the project of 'Research of On-Chip-Network Key Technology of Networks-On-Chip' supported by the Specialized Research Fund for the Doctoral Program of Higher Education (SRFDP,№:20050359003).The main work and achievement are as follows:1. The MPSoC platform was implemented at RTL, describing the design of On-chip Communication Architecture based on hierarchy bus. We verified the whole system and, some waveforms were presented here. From the results of verification we can see that the communication architecture satisfied the requirement of MPSoC platform.2. We write a pipelined-matrix-multiplication program using ARM assemble language and, co-simulation with the whole system. The matrix multiplication times is parameterized to generate different workloads. The result of experiment shows that when there are 4 processors and the multiplication cycle is 4 times, the speedup was only 2.2; with the increment of workloads the speedup came up to 3.2. We can draw the conclusion that with the workloads heavier, the speedup is going up, that is to say the cost of the communication between multiprocessors is diminishing.3. Prototyping the whole system based on FPGA. The whole system including hardware and software fits on the single FPGA. Experimental results had been obtained running at 60MHz with total area requiring 34% Adaptive Look-up Tables (ALUTs) and 17% on-chip memory of Altera Stratix II EP2S180.