NoC Test Ports Selecting Method And Research Of Dmesh Topology

Future Systems-on-Chip (SoCs) will integrate from several dozens to hundreds of cores in a single billion transistorchip, as the integration of SoCs become more and more compressional. Such systems will require communications templates with several dozens of Gbit/s of bandwidth, which still must be reusable to meet time-to- market requirements. Some recent works have proposed the use of integrated switching networks as an alternative approach to interconnect cores in SOCs. The overall idea is that such networks, also called Networks-on-Chip (NOCs) or On-Chip Networks (OCNs), meet the two key requirements for future systems: reusability and scalable bandwidth. It is expected that NOC-based systems will provide good solutions for flexible products that should be reconfigurable and programmable; for designs which are the basis for several products variants; for applications with a heterogeneous task mix; for applications with stringent time to market requirements; and finally, for products where reuse at the block, function and feature levels is considered valuable Therefore, it is clear that NOCs can potentially become the preferred interconnection approach for new SOCs. However, what it is still not clear is when the use of NOCs will become mandatory. In other words, the key question is: when should a design migrate from a simple and well known bus-based communication template to a new and more complex approach, such as NOCs.The main work in this thesis is as follows:(1) The test methods and topology of NoC are mainly introduced in this thesis. As the integration of SoCs become more and more compressional,the test of SoCs also become more and more important;The topology radically determines universal capability of NoC.So, the research of these two aspects is indispensable.(2) The first scheme presents an optimized test ports selecting method, which can determine the number and location of Input/Output pairs under power constraint. To make the length of all the core test paths shortest, the optimized location of the Noc test ports are selected. With the constraint of the max permitted power in the test, this scheme chose the number of the test ports pairs as large as possible. Thus the test of the cores is accomplished with high performance, and the apparatus damage in the test is avoided effectively as well. Experimental results show that the efficiency of the test is improved and the overall cost in the NoC test is decreased.(3) The second scheme presents a new toplology named Dmesh by connecting the diagonal of the 2-D Mesh and its routing algorithm called DXY.The DXY routing algorithm economizes the routing path, and the routing path become multiplicate.Experimental results by simulating the routing process of DMesh topology validates the conclusion.