Testing on-chip and multiprocessor interconnection networks and switches

Present trends in low-latency, high-bandwidth interconnects favour static, direct interconnection networks constructed from point-to-point VLSI routing components connected in mesh/cube, k-ary n-cube, or other regular low dimensional topologies. These direct networks support wormhole switching and virtual channel flow control. Such interconnects are used in many high performance scalable multiprocessor systems, to implement on-chip networks in System-on-Chip (SoC) designs and for designing high-performance switches. Due to their complexity these interconnects pose a significant challenge to effective testing. This thesis addresses the problem of testing low-latency, high-bandwidth direct multiprocessor interconnection networks as well as on-chip networks in SoCs and switches based on this technology. First we address the problem of testing direct networks having deterministic routing algorithms. We propose a (non-intrusive) functional approach for testing direct interconnection networks. We present a functional model, functional fault model and functional tests to detect the functional faults for a router in an interconnection network, and propose a theory for functional testing an interconnection network. Functional tests developed for an individual router can be extended to detect these same faults in an arbitrary instance of this router in an interconnection network. These extended tests, which are applied from the network inputs and observed at the network outputs, result in the appropriate router functional tests and test conditions being correctly set up and applied at the router in the network. A comprehensive case study of functional test development for a dimension order router is conducted to validate the effectiveness of the functional testing approach. This approach can be extended for testing networks with adaptive routing. We also consider the problem of design-for-test (DFT) for interconnection networks. We propose a DFT approach for interconnection networks based on extending the BALLAST partial scan methodology and applying it to the interconnection network. BALLAST is used for selecting scan registers in a self-connected version of each router in the network. For this DFT approach, test generation time, test application time as well as test I/O pin count remain constant as the network size scales.