Memory Encryption Architecture Technology Based On Memristor

Memory is the place where data is stored, and is also the last shield for keeping data secure. Thus, secure memory plays an significant role in information security. The problem of traditional secure memory technology lies in the separation of memory and processor. As a novel nanoelectronic device, the found of memristor and its recent research provide the possibility to integrate its memory function with its logic function. In this paper, we started from analyzing the classical encryption algorithms’ common operations, proposed the memory encryption architecture which features in the integration of both memory and operation functionalities. We investigated the approaches to implement the encryption algorithm using basic stateful logic of memristor, analyzed and designed the circuit structure which supports the merging of memory and encryption operation. We conducted comprehensive simulation to evaluate the system’s cost and performance.The main work and contributions of this part are as follows:1. Design of the memory encryption architecture based on memristor(Chapter 2)Based on memristor’s device characteristic that combines both memory and logic functions, this paper designed the memory encryption architecture based on mem-ristor. Without the need to read out data from nanocrossbar memory, we can di-rectly operate on the data stored in the memristor unit of the memory array through adding an encryption control block in the peripheral circuits of the nanocrossbar ar-ray. Such a encryption scheme greatly reduces the possibility of exposing data to the external threaten during the “data moving” process, and thus, will improve the mem-ory system’s security. Meanwhile, due to the natural parallelism of nanocrossbar structure, encryption process could be implemented on multiple wordlines within the same array and on multiple arrays in parallel, which will definitely improve the throughput of the encryption process.2. Design and optimization of the stateful logic operation sequence for basic encryp-tion operation(Chapter 3)According to the specific process of the basic encryption operations, including bit-wise xor, lookup tabel, shift, addition and multiplication, multiplication reverse in Galois field, modular multiplication and modular power, this paper presented the design and optimization method for obtaining the stateful logic operation sequence of these encryption operations. Combining the features of both memristor’s stateful logic and traditional digital circuit, we provided more than one method to implement each encryption operation, and gave the complexity of each operation. Through the analysis on each operation, we acquired many conclusions that are different from the design of traditional digital circuit, and also designed some particular logic func-tions for the above-mentioned architecture.3. Analysis and design of the stateful logic operation circuits based on nanocrossbar structure(Chapter 4)One important hypothesis for implementing encryption algorithm using stateful logic operation sequence on nanocrossbar is that the size and the operation must be scalable. This paper analyze the scalability of the circuit from both space and time dimension. In space dimension, we acquired an important conclusion that thresh-old voltage of the memristor device is the key parameter to maintain the scalability of the array. We also proposed the approach that makes use of the 1S1 R structure nanocrossbar to improve the spacial scalability. In time dimension, we showed that cumulative error in the existed operation circuits design may lead to fatal error. To solve this problem, we designed the self-adaptive reset circuit, which eliminates the error occurred by implication operation during the reset process. Such a design improves scalability of the stateful logic operation, while avoids the cost of extra refresh operation.4. Analysis and design of the reading and writing circuits for nanocrossbar memory(Chapter 5)In the reading circuits aspect, we proposed a multiplexed reading circuit for nanocross-bar memory. Compared with the existed reading circuit design, it could effectively reduce the cost of the peripheral circuits, and take better advantage of the mem-ristor memory’s high density property. Through the discussion on multiple circuitand device parameters, we concluded that adopting memristor with non-linear I-V characteristics or memristor with high LRS resistance could help to improve scal-ability of the multiplexed reading circuits. In the writing circuits aspect, we pro-posed a multi-level programming circuits for nanocrossbar memory. Without the need for extra selecting device, this circuit achieves precise programming of the memristor’s resistance by using the voltage threshold characteristic of memristor.Compared with existing research, this work could be adapted to a wide range of memristors that have been experimentally fabricated. We also designed a hamming network circuit based on the research of reading and writing a nanocrossbar memory. Compared with previous hamming network circuit, this design could achieve higher memory density with lower circuit cost.