Efficient And Reliable Stateful Logic Design Based On The Memristor

The rapid development of information technology has brought about the explosive growth of data.The traditional von Neumann computing architecture has some bottleneck problems,such as "power wall" and "memory wall".The future computing system must carry out comprehensive innovation on the underlying physical devices and computing architecture.The in-memory logic operation technology provides a historical opportunity to break through the bottleneck of von Neumann architecture,and the memristor provides a physical basis for the subversive development of in-memory logic operation technology.As the most representative technical path for logic operations in memristors,memristor stateful logic operations are currently facing the challenge of core bottlenecks such as single function of logic unit and complex structure of error correction methods.In this paper,the device characteristics of binary memristor are studied.Based on the characteristics of binary memristor,a new stateful logic operation unit and a stateful logic operation check and correction method are designed.The main work of this paper is as follows:In chapter 2,an efficient design scheme of memristor stateful logic operation unit is proposed.Firstly,three kinds of basic logic which can be realized in parallel structure of double memristor are introduced,and 16 kinds of basic Boolean logic are realized in cascade mode(Section 2.1).Then,three other kinds of basic logic that can be realized in the double memristor inverse parallel structure are introduced(Section 2.2).Finally,the feasibility of the designed logic is evaluated based on the existing device performance(Section 2.3).The experimental results show that the basic logic unit designed in this chapter has obvious advantages in the number of devices,operation steps and other aspects,and is of great significance for the realization of complex logic operations in the high-density 3D integration environment.In chapter 3,a highly reliable error detection and correction method for memristor stateful logic operation is proposed.Firstly,the occurrence regularity and regulation approach of logical errors are analyzed,and a method of error correction for single error type is proposed(Section 3.1).Then,the validity of the proposed error-correcting method is simulated and verified by a memristor cross array chip test(Section 3.2).Finally,the advantages and disadvantages of this work are summarized(Section 3.3)by comparing this work with the existing stateful logic operation unit error correction methods.Experimental results show that the proposed method can effectively improve the accuracy of logic operation.Compared with existing methods,the proposed method has the advantages of fewer devices,fewer steps and less dependence on peripheral CMOS circuit.In chapter 4,a design scheme of one bit full adder with self-correcting function based on memristor is proposed.Firstly,the implementation principle and implementation steps of one-bit full adder based on implication logic are introduced(Section 4.1).Then,by means of simulation,the influence of non-ideal factors of actual devices on the operation accuracy of the full adder is analyzed(Section 4.2).Finally,a one-bit full adder is simulated and its self-correcting function is verified by checking and correcting the main logical operation steps(Section 4.3).Experimental results show that the self-correcting function of the full adder can effectively suppress the influence of non-ideal factors and significantly improve the operation accuracy of the full adder,which provides a reference for the design of memristor based arithmetic operation unit error correction.