Multi-standard High Performance Forward Error Correction Processor

In the era of multi-standard wireless communication, many standards need to be supported in a single chip in wireless terminals. The Forward Error Correction(FEC) also referred to as channel decoding varies in these standards in terms of algorithms and configuration parameters. In this work, a highly flexible multi-standard FEC processor is investigated and designed for nowadays mainstream and future wireless standards. In current high speed communication standards, the coding schemes mainly include QC-LDPC, Turbo and Convolutional code. Thus this work focuses on these three types of codes.The research mainly innovates on several aspects following.First, this work investigates the attributes of these three types of codes, and the execution flow and computational similarities are abstracted. Then the tri-mode unified decoding framework is established. The unified forward-backward recursion method is proposed for tri-mode decoding. The formal expressions in equations are provided. This method is applied as the basic principle of the hardware resource merging and processor architecture design.Second, the hardware resource sharing is investigated for reducing the silicon cost. The investigation is performed in three aspects including the shared memory sub-system, merged data path and unified control logic. The architecture is designed by merging as much resources in independent modes as possible. The reduction of memory resource cost and logic resource cost is also investigated.Third, the flexibility is improved with the high speed high parallelism architecture, and the architecture is designed for supporting as much standards as possible. As a result, the proposed decoder supports the largest number of standards worldwide. Currently the supported standards include 3GPP LTE/WCDMA/HSPA Turbo, 802.11n/802.16 e QC-LDPC and multi-standard Convolutional codes. The proposed processor is in highly symmetric architecture, and therefore easy to be expanded for higher parallelism, which is needed for future high throughput decoding.Fourth, a Single-Instruction-Multiple-Data(SIMD) application-specific processor architecture is proposed, which is dedicated for supporting the parallel forward-backward recursion algorithms. The decoding flow expressed by the proposed application-specific instruction-set is simulated by software model with clock cycle accuracy. Thus the programmability is enhanced. The feasibility of expanding it to a fully programmable architecture is investigated, with the objective of programmability to improve the market-time of the baseband processor and to reduce the chance of tape-outs.Fifth, several techniques are proposed for improving the efficiency of the proposed architecture, including the conflict-free Turbo decoding with arbitrary interleaving patterns and arbitrary degree of parallelism, the matrix reordering techniques for LDPC read-after-write conflicts, and the path metric storage method for Viterbi decoding with arbitrary trellis sizes. In addition, the multiple nested loops that exist in the decoding flow are accelerated by the self-loop instructions and hardware loop acceleration circuits.Sixth, the processor system architecture is implemented. The instruction set, hardware RTL description, and processor cycle accurate model are provided, the chip is placed and routed using 65 nm CMOS technology, and the silicon consumption results are provided in detail. It reveals that the proposed decoder precedes other alternatives worldwide on several aspects, including the decoding efficiency per cycle, silicon area, Turbo decoding throughput etc.Seventh, the computational complexity of the decoding algorithms is investigated for the software defined radio and fully programmable platforms. The analysis is derived from the algorithms, and the hardware friendly pseudo-codes are proposed. The operations of decoding stages are analyzed and the guideline for the minimum number of operations is proposed for these three algorithms. The computation platform requirement for future higher throughput decoding is predicted. The proposed results are compared with nowadays software oriented decoding platforms. The results and analysis are prone to be applied for software defined decoding platform selections and optimizations.