Multi-mode Multi-standard Baseband Processors Forward Error Correction Code Decoding

The thesis is about the algorithm and reconfigurable architectures of both Turbo code and LDPC code.The performance of Turbo and LDPC are near Shannon limit and they are widely used in communication.A Turbo decoder suitable for Wimax standard is proposed.The BER of the decoder can achieve 10-6@0.90db by employing the MAX-LOG-MAP with corrector algorithm.The memory requirement of the architecture reduces 35%by removing the redundancy of variables and rescheduling the decoding procedures.The performance of the decoder can also achieve 10-6@0.95db after 6-bit quantizing.Base on SIMC 0.13um,the proposed Turbo decoder has an estimation area of 1.76 mm2 with 6-bit quantization and a throughput of 12.4Mbps with a frequency of 100MHz and the iteration number of 8.In this paper,a generic architecture for QC-LDPC codes decoding is proposed.The novel architecture can perform decoding of multi-standard LDPC codes with multiple rates and variable lengths by introducing a special binding schedule and a scalable shuffle network.The new memory arrangement improves usage efficiency of memories as many as 13 times.A scalable data exchange network is proposed to regularize wire connections, which efficiently reduces the interconnection complexity.The proposed novel architecture can achieve the goal of decoding LDPC codes with multiple rates and variable lengths at a cost of what a LDPC decoder with single rate and invariant length consumes.The scalable shuffle network not only reduces the interconnection complexity,but also breaks the constraint of invariant lengths.The flexible decoder is compatible for LDPC codes applied in a multi-standard system.Based on SMIC 0.18um standard CMOS process,the LDPC decoder for Chinese DTMB standard and Wimax standard has an estimation area of 8mm~2 with 8-bit quantization,and a throughput of 91Mbps with a frequency of 50MHz and maximum iteration number of 15.