Research And Design Of Reconfigurable Baseband Platform For Wireless Communication With Typical Algorithms Implementation

The rapid development of wireless communications generates the multi-standard/multi-mode market, and it will stay for a long time. With the increased requirement of the multi-mode processing ability, the academic and the industry are trying to find good resolutions. The recently developed Software Defined Radio (SDR) technology is one of them, and is now widely accepted. As one of the important part of SDR, the multi-mode baseband processing circuit is one of the challenging topics within the digital VLSI design area. The research on it will powerfully improve the development of SDR industry. Based on the reconfiguration idea, this dissertation proposed a reconfigurable baseband platform for wireless communications, and implemented several typical algorithms and systems.In this dissertation, we summarized the structure features of the current reconfigurable processor as well as their inefficiency in wireless communication area. Aimed at these points, we firstly analyzed some currently widely used communication systems as well as some systems which will be used in the coming future, such as RFID, WLAN, and MIMO systems, including the baseband algorithms and processing flow; summarized and abstracted the basic calculation types which can cover most of the mainstream algorithms. We have carefully designed the reconfigurable execute units for each of the calculation type, and composed the function oriented, heterogeneous, and coarse-grained reconfigurable execute core. Based on the data flow, we also proposed the hierarchical interconnection and storage structure as well as the static-configured and multi-bus global switch. In the system control, this thesis presented a novel FFT address generator which can give various sizes of address. Meanwhile, we have established the generation mechanism for config-information; and furthermore, we have built a whole reconfigurable processing platform.In this dissertation, several algorithms and systems are implemented on the platform, including the RFID interrogator baseband based on EPC Gen2 protocol, the multi-mode Fourier Fast Transform (FFT) and Space-Time Block Decode (STBD) used in MIMO-OFDM system, and the adaptive Uniform Channel Decomposition (UCD) and Space-Time Block Coding (STBC) system. The implemented algorithms and the computing scale are different; therefore, this thesis has well verified the platform from different aspects. Meanwhile, there are the considerations of the mapping algorithms and methods optimization for further performance and efficiency improvement. Therefore, in FFT implementation, the super-point idea is used to reduce the memory access frequency; in STBD implementation, the sign detection approach is used to reduce the search area and to save the configured resources; in the UCD/STBC system implementation, the adaptive modulation idea is used to balance the data transmission quality and rate.Finally, as one important part of Forward Error Coding (FEC) module and the supplement of the platform processing ability, in this dissertation, a bit reduction LDPC decoder has been developed. This decoder uses the layered decoding structures and hierarchical storages as well as the signal control logic which is similar to Finite State Machine (FSM) and makes the data storage and signal routing much easier.