Design And Implementation Of A Flexible Mpsoc For MIMO Interference Cancellation

Wireless communication systems have been experiencing massive growth in terms of traffic and devices volumes for the last two decades.To fulfill the demand from the market,many wireless protocols have evolved several generations during this period,which results in the coexistence of different protocols belonging to various generations.Traditionally,each protocols requires a specific hardware system.However,this approach is no longer feasible anymore for current situation.In order to save cost and reduce the time-to-market,future smart devices demand flexible platforms that are able to support various protocols and soft update.Aiming to the most demanding and varying part of the MIMO baseband processing,interference cancellation,a heterogeneous multi-core processor is proposed,designed and implemented based on a top-down approach.Firstly,we test the performance of various typical interference cancellation algorithms under a close to physical environment simulation platform,and then,we comprehensively analyze these algorithms in terms of parallelism,communication patterns and computation patterns.After that,following the divide-and-conquer(D&Q)strategy in terms of hardware,we propose a heterogeneous multi-core architecture which consists of one flexible master core and several flexible slave cores based on the division of computing and control of the mapped algorithms.Moreover,two specific instruction sets are designed for the master core and slave core respectively.To verify the feasibility and flexibility of the proposed architecture,several interference cancellation applications are mapped on this architecture following the same D&Q strategy in terms of software.Finally,the synthesizing results and one layout implementation of the proposed architecture are also presented.The main contributions of this dissertation are highlighted as follows:1.For the performance test of interference cancellation algorithms,in order to build a simulation platform close to the physical environment,we construct a multi-user MIMO OFDM simulation system based on the newly released IEEE 802.11 ac standard and its wireless channel models.Moreover,we also test the functionality of the simulation system within real indoor channel condition based on the WARP(Wireless Open Access Research Platform).Based on the above simulation system,we test several typical interference cancellation algorithms under perfect and noise channel state information(CSI)condition.In addition,by statistically modeling the errors caused by channel estimation and feedback delay,a flexible low-complexity compensation method for THP with imperfect CSI is proposed.2.For the architecture design,aiming at the tested algorithms,we comprehensively analyze these algorithms in terms of numerical precision,parallelism,communication patterns and computation patterns.The common computation patterns and communication patterns are abstracted to guide further architecture design.According to the analysis results,a low-complexity and flexible ad hoc point-to-point interconnection network based fine-grained programmable-element(f-PE)is proposed to execute the concrete arithmetic calculation.Different computation patter can be achieved by adjust the routing paths among the registers associated with each primitive unit.Moreover,in order to assist the f-PE,we integrate one I/O unit to communicate with other nodes and global storages,one local register file(RF)and one local instruction unit to exploit the data and instruction localities in the slave core.In addition,a specific sorting system is designed in the master core to accelerate the sorting operations required by the non-linear interference cancellation algorithms.Finally,a collaboration system to coordinate the master core and slave cores is designed based on FIFO buffers and interrupt system.3.For the programming,to make this heterogeneous architecture easy to use,based on the D&Q strategy in terms of software,we design two specific instruction sets for the master core and slave core respectively.On the one hand,the programming method on the slave core is similar with the soft pipeline.One computation patter are accomplished ny multiple instructions while each instruction performs different stages of several computation patters simultaneously.On the other hand,the programming method on the master core adopt a VLIW(very long instruction word)-like fashion.To justify the flexibility and feasibility of the proposed architecture,several application with distinctive computation natures are mapped on the architecture,including linear matrix inversions and sophisticated non-linear sorted QR decomposition aided THP algorithm.As far as we know,this is the first implementation of the SQRD aided THP on hardware.4.Finally,the synthesizing results show that the maximum achievable frequency is535 MHz.Additionally,a layout implementation of the architecture under 400MHz are presented,which consumes 271 k equivalent gates and 0.935mm2 logic area.Compared to the state-of-art works,the proposed architecture achieves the best flexibility at the cost of acceptable area consumption,which can support various computation patterns and applications.Compared to other programmable architectures,the proposed architecture can achieve better hardware utilization efficiency,less computation delay and lower power consumption.Although this architecture is originally aimed at MIMO interference cancellation algorithms,we believe that our architecture is of great flexibility potential to support more algorithms.