Characteristic Study And Design On Electronics Discharge Circuit And Device Of Integrated Circuit In CMOS Processes

With the development of semiconductor industry, especially the decrease of the feature size of CMOS process and the addition of varieties of new technology steps, semiconductor devices become vulnerable. However, people’s expectation of high circuit performance makes it more difficult to design the electronics discharge(ESD) protection circuit. In the dissertation, the circuit-level and device-level ESD design in both micro and nanometer CMOS processes are investigated. Test, failure analysis, devices and circuit design are also reviewed. The main content is as follows:1. In this dissertation, the basic concepts of ESD are reviewed, including the production of ESD, test model, test method, failure analysis and common protection methods.2. The ESD devices are studied and modified. First, the several main ESD devices are reviewed and compared, their advantages and disadvantages are both analyzed, and the existing issues are also discussed. Furthermore, the attractive device SCR is investigated, its important issues, such as trigger voltage, holding voltage and parasitic parameters are discussed. Last, the SCR is optimized by simulation.3. Design of ESD clamp circuit. ESD clamp circuit is a crucial part of the whole chip ESD protection. In Chapter 4, firstly, the classic RC triggered clamp circuit is discussed, the application and operation principle of RC network in ESD clamp circuit are introduced, and the suitable RC time constant for distinguishing the ESD event and normal operating conditions are derived. Secondly, in a 0.18 μm technology a double pull-down path structure to reduce RC time constant is proposed, and the layout area is decreased as well. In 90 nm technologies, the gate leakage current issue becomes significantly, so the mechanism and effect in RC power clamp are introduced. After discussed several solutions in recent references, we also present two, one using leaky characteristic of gate to trigger SCR and the other using modified RC network. At last, the voltage triggered ESD clamp circuit is introduced, which is immune to the false triggering, but its trigger efficiency is not as high as people expected. Therefore, we proposed one with feedback to enhance the trigger efficiency while avoiding latch-up by adding a modified RC network, and the addition of layout area is very small.4. High voltage tolerant clamp circuit is widely used in So C. Since we should guarantee that the circuit has high protection ability and also make sure the circuit can sustain high voltage stress, the design becomes much more complex and difficult. In this dissertation, firstly the concept of whole chip protection of high voltage tolerant circuit is introduced, the two existing structures are compared and their disadvantages are discussed, and in turn the concept is modified. Afterwards, the recent high voltage-tolerant circuits are evaluated, based on these techniques, a circuit in a 0.18 μm process is optimized, and two new circuits in a 90 nm process is presented. The first one in the 90 nm process is developed from the circuit triggered by leaky characteristic, which is introduced in Chapter 4. The other one saves fabrication cost since it does not need deep N-well step.In summary, based on general CMOS technologies, the ESD protection device SCR, power clamp circuit, and high voltage tolerant clamp circuit in micrometer and nanometer processes are analyzed. Several modified designs on device and circuit structure are presented, and some meaningful results are obtained.