Research And Design Of Analog Neuron Circuit For Computing-in-memory SCNN

In recent years,with the rapid development and wide application of deep learning,the convolutional neural network(CNN)has obtained more and more studies and applications in the fields of image and speech recognition.The increasing network layer number and scale have dramatically increased the data amount for convolutional operations.The traditional Von Neumann architecture is unsuitable for such application scenarios as neural networks because of the so-called memory wall.The computing-in-memory(CIM)spiking convolutional neural network(SCNN)based on NOR flash shows remarkable performance in high image recognition accuracy and low power consumption,which may help to solve the memory wall problem.As the basic component of CIM SCNN,neuron circuit replaces the analog to digital converter(ADC)in the CNN,responsible to read out the array current and convert them into a series of voltage pulses.Therefore,the neuron circuit has become a key factor for improving the performance and accuracy of SCNN.In this thesis,according to the current research trend of neuron circuit,an analog neuron circuit based on the CMOS technology is studied and designed to meet the requirements of CIM SCNN,which provides a complete peripheral circuit architecture and performance enhancement solution for CIM SCNN.The main research content of this thesis can be summarized as follows.Firstly,the hardware architecture and working principle of SCNN based on NOR flash are described.A complete analog neuron circuit is then designed according to the function and performance requirements of SCNN,including the bit line(BL)clamp circuit,current readout and subtraction circuit,spiking neuron circuit and voltage bias circuit.The bit line clamp circuit realizes the voltage clamp function of the array and helps to complete the multiply-accumulate operation.The current readout and subtraction circuit realizes the readout and subtraction of the array output current and the convolutional operation in the analog circuit.The spiking neuron circuit realizes the integral of subtraction circuit and converts the current signal to a series of voltage pulses with fixed amplitude.The voltage bias circuit is responsible for providing the bias for other circuits.A circuit pre-simulation platform is built,and the simulation results show that the analog neuron circuit works normally.In order to fully evaluate the circuit performance,some key performance indices are proposed for the neuron circuit,which can provide a optimization direction for the circuit design.Secondly,the performance optimization and function improvement of the analog neuron circuit are carried out by using the proposed performance indices.A new bit line clamp circuit architecture is proposed to reduce power consumption,time delay,and bit-line voltage fluctuations in a wide current readout range while remaining the high-accuracy clamping.A new by-pass current system is added to the current readout and subtraction circuit to improve the readout speed and readout range by selecting different combinations of by-pass currents according to the performance requirement of SCNN.In order to avoid the array information loss due to the traditional analog neuron reset method,a new reset scheme with subtracting threshold voltage is proposed to improve the integrity of information and the accuracy of neural network.A new spiking neuron circuit with adjustable threshold voltage is proposed,which can realize the online adjustment of threshold voltage in the chip.Thirdly,the layout design and the post-simulation verification of the designed analog neuron circuit are carried out.The layout area is about 0.0042 mm~2.Under a 1.2 V power supply voltage,the post-simulation results indicate that,in the current output range of 0-20μA,the bit line voltage error can be controlled within 0.4 m V and the fluctuation is less than0.31 m V.The current readout speed is improved by 263.6%and 100%at 0μA and 20μA,respectively.The reset scheme with subtracting threshold voltage functions properly,and the error is less than 1 m V.Results demonstrate this work provides a complete and efficient peripheral circuit hardware solution for SCNN based on the NOR flash array.Finally,in order to further evaluate the impact of circuit performance on neural network recognition accuracy,the circuit model of behavioural and performance parameters are taken into the Alex Net and Le Net algorithms for testing.The test results show that the network recognition accuracy only decreases by less than 0.3%with the circuit model.Furthermore,with the new reset scheme,the recognition accuracy of Alex Net for the CIFAR-10 dataset and Le Net for the MNIST dataset is improved by 38.8%and 1.4%,respectively,exhibiting an obvious improvement effect.