The Study And Design Optimization Of Electrostatics Discharge Network And Device Characteristic In Integrated Circuit

With the increasing development of semiconductor industry, especially when new process is introduced and the scaling down of characteristic size, integrated circuits and system become more and more sensitive to ESD pulse. This dissertation analyzes the characteristics of ESD protection methods and their simulation results, and design network of basic ESD clamp circuit based on 0.35 um CMOS technology. With the help of experiment of JSR26C32 designed by SMIC and CD54HC123F3 A by TI, we have analyzed the reason of their failure and gave some useful suggestion. The main research as follows:In this dissertation, the basic concepts of ESD are reviewed. Basic characteristics of four types of ESD protection devices are studied and simulated. Emphases are put on the current and heat distribution of gg NMOS under the pressure of ESD. The trigger voltage and hold voltage of SCR and LVTSCR structure are compared by TCAD simulation.Rail-Based ESD networks consisting of active MOS and related RC timer are studied. Different level of coupling capacitance between gate and drain simulated by HSPICE are compared to provide theoretical proof for circuit design. Then we propose a better clamp network aiming at the application of multi-supply domain. This network can reach a high tolerance voltage based on two stacking MOS devices to achieve a double clamp voltage. Simulation work has proved that its actual clamp voltage can achieve about 10 V level. At last two-stage protection strategy applied both in Rail Base and local clamp network is studied. A three-terminal diode device formed two stage protection circuit is simulated to verify that there is a proper difference voltage between PAD and internal node.The experiment methods for the chips named JSR26C32 provided by Shanghai Academy of Spaceflight Technology and CD54HC123F3 A of TI are designed. And detailed ESD protection circuit scheme and layout are analyzed. Testing methods are made for three modes: HBM, MM and CDM, including initial test voltages and step sizes, at last the final ESDV of three modes are worked out. Three different criterions are proposed to determine whether a chip functionally failure. With the help of optical microscope and other devices, we have found out the failure devices. Then continue to dissection to find out their exact position and analyze the failure reason by studying the scheme and layout. Finally we have consulted both domestic and international advanced experience to propose some solutions to improve its circuit and layout.In conclusion, this dissertation is based on basic methods of designing of ESD protection device of gg NMOS and SCR. The performance of basic clamp network and high voltage tolerance network are analyzed and simulated. With the help of scheme and layout, we analyze the final failure reason of both chips and give some advice for follow-up work.