Development Of The FPGA-Based Control Logic And Circuit In Data Acquisition System For Patch-Clamp

The Patch Clamp Technique has become an important tool for electrophysiological research. The data acquisition and control interface, which connects the patch-clamp amplifier and the personal computer, and realizes the communication of the data and the control commands, is the data transmission hinge of the patch-clamp system.This design used USB 2.0 (Universal Serial Bus 2.0) and FPGA technique to improve the original system UDA-1 data acquisition. By using the FPGA, the new system has accomplished not only the synchronization between data acquisition and signal output, but also the independence of analog input and output. With two FIFO memories integrated into FPGA, which have asynchronous clock domains, the circuits were simplified and the system stability was improved. It is quite a reasonable design for data acquisition system at present.Beginning with the system architecture, this thesis was focused on the firmware of CY7C68013 and the control logic of FPGA. Then, USB2.0 interface, FPGA configuration and circuit design were also described. In addition test results and prospect were mentioned in the end.