The Research On Fabricating SOI、SGOI、 GOI Materials

Along with the continuous development of the microelectronics technology, feature size of the semiconductor device scaled down from 65/45 nm to 14 nm, and in the near future it will develop to the 10/7 nm node. However, improving the performance of current mainstream CMOS devices using the scaling rule has encountered more and more physical and process limitations. The technology of integrated circuits needs some significant changes, such as designing novel device structure and introducing advanced channel materials. In recent years, strained Si has been widely used as the channel material due to the high carrier mobility. According to ITRS, in 2016-2020, the conventional Si will be replaced by Ge/III-V materials as the channel material.Under the above backgrounds, the research work in this thesis mainly focuses on: (1) Study of fabricating 8 inch strained Si, SiGe and Ge films on Si substrate; (2) Fabrication of 8 inch ETSOI, sSOI, SGOI and GOI materials by the layer transfer technology; (3) Developing a novel layer transfer technology—the Simsplit technology; (4) Analyzing the H trapping and layer split mechanism of the Simsplit technology; (5) Study of the factors affecting the layer transfer effect in the Simsplit technology. The main results are summarized in the following:1、The epitaxy technique for strained SiGe films was systemically investigated. It is found that the SiGe layers growth rate and Ge composition depend on GeH4 flow, deposition temperature and reactor chamber pressure. Based on this research result, high quality 8 inch SiGe films have been achieved.2、The two-step growth approach [low temperature (LT) and high temperature (HT)] combined with low temperature buffer layers has been applied to grow high quality Ge layers on Si substrate. The obtained Ge epilayer shows excellent surface morphology (RMS<0.5 nm), low TDD (on the order of 106 cm-2), and a homogeneous distribution of tensile strain of 0.24%. It established foundation and provided material for the fabrication of GOI wafer.3、Using the 8 inch strained SiGe, sSi and Ge films as donors, the SGOI, sSOI and GOI wafers have been successfully fabricated by Smart cut process. The testing results show that the obtained SGOI, sSOI and GOI materials have high crystal quality with smooth surface morphology (RMS<1 nm) and low TDD (on the order of 105cm-2).4、Based on the high H trapping efficiency of B-doped SiGe layers, we developed Simsplit technology with independent intellectual property right. When B-doped SiGe layer is incorporated, continuous cracking along the strained SiGe layer can be achieved with H implantation fluence as low as 3×1016 cm-2, which is only half of typical implantation fluence for the ion-cut process. Furthermore, since the unique cracking is completely confined within the B-doped SiGe interlayer, the as-cut SGOI wafer possesses a rather smooth surface even without any CMP process.5、Through a series of film split experiments, the mechanism of Simsplit technology was explained from four aspects:the bond energy, the shear stress, the stress release rate and the defect evolution process.6、Further study illustrated that the H trapping efficiency relies on Ge composition in SiGe layer, annealing temperature, implanted energy, and SiGe interlayer thickness.7、The B-doped SiGe/Si superlattices interlayers and microwave annealing were introduced in Simsplit technology to enhance the trapping efficiency.