The Design And Study Of Optical Network-On-Chip Based On Storus

With the increase of communication traffic, the research on high performance processor becomes popular. Especially in the recent years, Network-on-Chip(NoC) performs better and better in data movement, and more and more IP cores are integrated into a single chip. However, as more IP cores integrated in a single chip, NoC, which is based on electrical interconnect, faces many problems, such as high end-to-end delay, optical loss, electromagnetic interference and so on. While the progress of Silicon photonic technology and nano photonic devices make Optical Network-on-Chip(ONoC) come ture. ONoC can solve the high end-to-end delay, on bandwidth, electromagnetic interference and the other problems that exist in NoC.This thesis introduces the rise and development of NoC, and analyzes the advantage of Optical Network-on-Chip. Then the thesis studies the research of ONoC, including optical devices, switch mechanism, routing algorithm and the topologies in detail. Many new topologies are based on mesh and torus, thus the diameter, loss, chip size and many other aspects perform bad. In order to solve these problems, STorus, a new topology is proposed. STorus takes the hop count, diameter, optical loss and many other terms into consideration. Two subnets are employed, and each subnet adopts two screwy rings, which decrease the diameter and hop. In terms of layout, STorus uses Through Silicon Via(TSV), the waveguides that belong to the same direction are located in one optical layer, and there are two optical layers in all. OPNET is used to simulate the STorus, and a comparison between STorus, mesh and torus is made. The result shows that STorus performs well in optical loss, diameter, end-to-end delay and throughput.The amount of memory access increases with the increase of the number of integrated IP cores in a chip, which limits network bandwidth. If the bandwidth can not meet the requirement of requests from IP cores, network performance would be influenced. Therefore, we study the influence of memory controller's access location, and optimize the location of memory controllers. The simulation result shows that under the same number of memory controllers, the network using optimized location performs better than the other with the same scale.