Research On Memory Controller Layout Method For Network On Chip

As the number of processor cores integrated on Chip Multiprocessors(CMP)continues to increase,Network-on-Chip architecture has been proposed as a promising interconnect technology for CMP.There is a higher demand for memory bandwidth during parallel execution of multiple processor cores,and memory bandwidth between processor cores and off-chip memory becomes a critical issue("bandwidth wall"problem).Integrating more memory controllers on a chip is an effective and feasible way to solve this problem.Different layouts of memory controllers can have different impacts on system performance.How to place multiple memory controllers for network-on-chip becomes an important issue.Previous studies have been time consuming,or lacked theoretical analysis,or limited in scope of use,so it is important to design an efficient layout method.After analyzing the delay of memory access procedure,it is found that different layouts of memory controllers will lead to different delay of memory access,especially contention delay in on-chip communication process.We will focus on how to quantitatively express contention delay.If contention delay can be replaced with some simple indicators proposed and then an efficient calculation method based on the proposed indicators is presented,then different schemes are proposed to place multiple memory controllers.Based on the above ideas,this paper proposes two surrogate indicators:link busy factor,path load factor,and designs their corresponding two-stage calculation method,then proposes a layout evaluation criterion based on proposed indicators.On this basis,the optimal layouts corresponding to different network scales and different number of memory controllers are found for different memory controller types.The main work and innovations of this paper are as follows:Firstly,the delay of memory access request is analyzed.This paper analyzes which part of the delay component will be affected by different memory controller layouts,and finds the most affected delay component--contention delay.Secondly,we proposed two surrogate indicators:link busy factor and path load factor.The link busy factor can quantitatively indicate how many messages compete for each link,and then it can be used to represent the contention delay of messages on each link in the on-chip communication network.The path load factor can quantitatively indicate the sum of contention messages on all links,and all links include links through which memory request sent by processor core to memory controller pass and links through which memory reply sent back by memory controller to processor core pass.This value can then be used to represent the whole contention delay on the roundtrip path of memory access request.Thirdly,for the two proposed indicators,a two-stage calculation method is designed,and the average path load,which is a layout evaluation criterion based on the surrogate indicators,is proposed.For the proposed indicators of link busy factor,we design the link busy factor labeling algorithm in the first stage.For the proposed indicators of path load factor,based on the results of the link busy factor labeling algorithm in the first stage,we design the path load counting algorithm in the second stage.Finally,for two different types of memory controllers,i.e.separate memory controllers and integrated memory controllers,we respectively find the optimal layout corresponding to different network scales and different number of memory controllers.The experiment using OPNET simulation platform shows that the memory controller layout found by the proposed method has lower network latency and higher network throughput than other layouts.At the same time,we found more optimal layout schemes.Additionally,it is helpful for future CMP design.