Performance Evaluation And Optimization Of On-chip Memory Controller

Memory system is the bottleneck of performance improvement for modem computer systems. Over the past twenty years, advances in microarchitecture and process have produced an annual increase in processor speed of 60%, whereas DRAM speed has only an increase of approximately 10%. Industry and academic community are always making their endeavor to narrow the gap caused by the imbalanced development of microprocessor and memory' devices. Recently in hardware architecture emerges three novel technologies, which probably will provide chances and challenges for memory system optimization: DDR I/II SDRAM, On-chip Memory Controller, Multicore and Multithreading.This paper focuses on the evaluation and optimization of on-chip memory controller, with the consideration for the characteristics of Godson II microprocessor. The main contributions of this paper are as below:Performance evaluation method based on statistical clusteringA fast and accurate performance evaluation environment/method is the precondition for any subsequent optimization. In hardware design field, software-based simulators are becoming a tool of importance for performance evaluation, but their speed is many orders of magnitude slower than the hardware simulated. We present a fast simulation method based on statistical clustering, which significantly reduces the simulation time of SPEC 2000 from 10 days to 40 minutes with error ratio smaller than 5%. We employ this method in the subsequent performance evaluation of on-chip memory controller.Memory access scheduling in on-chip memory controllerThe advantage of on-chip memory controller to access the large miss queue in the processor core greatly increases the potential for memory access scheduling. We first compare the influences on the page locality of conventional address mapping and the XOR method in DDR SDRAM, which only has 4 or 8 banks. We then discuss the memory scheduling strategies with the interaction of page management in single core processor, and at last we analyze the issue of memory access balance in CMP. The experiment results show that compared with open page mode, memory scheduling will increase the average IPC of SPEC 2000 roughly 8%. Memory bandwidth of the STREAM benchmark has 23% improvement. For some combination of multicore applications, balanced memory scheduling will improve the system overall performance about 7%.