Design Of An On-chip Optical Network For Memory System

The emergency and design of processor with multi-cores make it possible to gain exaFLOPS(exa Floating-point Operations Per Second) computing in 2020. With the number of cores increasing, the demand for designing a high-bandwidth low-latency core-to-memory network becomes more apparent. During the communication procedure between cores and memory, the electronic based interconnects faces great data transmission power consumption and wiring difficulties when data rate exceeds. Furthermore, memory access latency and access bandwidth of electronic bus-based interconnect are becoming the bottleneck in improving system performance. High-performance computing system will face the problem called “memory wall”.By using 3D integration, cores, memory modules and the on-chip optical interconnect network can be integrated into a single chip. In this thesis, taking advantages of deposited silicon photonics technology, our work emphasizes on the design of an optical on-chip interconnect network, aiming at increasing the parallelism of core-to-memory communication.Firstly, we analyze the traffic characteristic of core-to-memory communication. Based on the traffic characteristic, we propose a scalable optical on-chip network topology serving the communication between cores and memory system. In order to access the memory system parallel, memory modules of the memory system are divided into several “ranks”. A rank is defined as the minimum parallel accessible memory unit. In this topology, cores and ranks are connected with each other through a set of annular waveguides. A core sends transactions to different ranks through different annular waveguides. Transactions from different cores are distinguished by different wavelengths in an annular waveguide. By arranging the wavelength resources and micro-ring resonators delicately, the parallel non-congestion communication between cores and ranks can be realized.Secondly, the core's and rank's network interfaces are studied. Buffer counters are placed into rank's interfaces, which is used to monitor the process of transactions. When the counter's value reaches a threshold, the rank's interface will broadcast messages to all cores through the proposed network. In this way, memory access traffic can be controlled and transactions will not be discarded. A pipeline-like distributed memory controller is also integrated into core's and rank's interfaces. Transaction address can be parsed concurrently in the distributed memory controller, which shortens the memory access latency.Finally,memory access traffics of applications from PARSEC benchmark are extracted and used for evaluation. The proposed optical on-chip network and traditional electronic bus-based interconnect are simulated. Simulation results show that when connecting 4 ranks memory system, the average bandwidth of the proposed network is 1.9 times higher than that of the electronic one. The average number of transactions executed during the simulation in the proposed network is 1.95 times larger than that of the electronic one. The average latency of proposed network is only 46.8% of the electronic one's. When connecting 8 ranks memory system, compared with the electronic one, 2.63 times higher bandwidth and 2.52 times larger number of executed transactions can be achieved. The access latency is only 10.2% of the electronic one's. The energy consumption analysis shows the energy consumed by transmitting one bit data in the proposed network is much lower than that in electronic bus-based interconnect. In summary, on dealing with the memory access bottleneck in future high performance computing systems, our work shows great perspective.