The Design And Simulation Of On-Chip Optical Interconnect Architectures

A large number of IP cores will be included in the future systems-on-chip (SoC). Traditional bus-based architectures are no longer suitable for modern chip design, since it is difficult to expand and consumes much power and much area. Network-on-chip (NoC), which employs networks to replace buses as a scalable global communication platform, has been proposed to cope with these problems. However, limited bandwidth, long delay and high power consumption will become bottlenecks as NoC scales to large sizes. Based on silicon optical interconnect, optical network-on-chip (ONoC) can offer significant bandwidth and power advantages, which provides a promising solution to overcome these limitations. In this thesis, we simulated and compared performance of several ONoCs based on the topologies including Mesh, Fattree (FT) and Butterfly Fattree (BFT). Based on the advantages of Mesh and Fattree, we proposed a new ONoC called Fattree of Mesh (FoM) including its topology, floorplan, addressing and scaling. We also designed a new routing algorithm suitable for FoM, simulated and compared several ONoCs based on the topologies including Mesh, Fattree (FT) and Butterfly Fattree (BFT) in terms of the end-to-end delay, network throughput, and area and power consumption. The results showed that FoM has certain comparative advantages in terms of network performance and cost among the listed topologies.