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Optical Network On Chip Architecture And Control

Posted on:2020-07-11Degree:DoctorType:Dissertation
Country:ChinaCandidate:W Z LiFull Text:PDF
GTID:1368330572972119Subject:Electronic Science and Technology
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With the development of information technology and semiconductor tech-niques,The number of IP cores integrated on chip multi-processor has increased significantly,and the communication has increased as well,which presents higher requirement on performance of interconnection network in terms of de-lay and bandwidth.In traditional multi-core chip system that based on bus structure,there is higher signal delay and power consumption,and IP cores will compete frequently for the communication resources.So Bus structure can not fulfill the increasing requirement of multi-core chip.Recently,the break-throughs in silicon phonics make it possible to implement the optical network on CMP.Optical interconnection has higher bandwidth,lower delay,and lower power consumption,and once optical path is established,the end-to-end trans-mission don does not consume extra power.These advantages make optical network on chip(ONoC)became a attractive platform.As the improvement in performance of future multi-core system mainly depends on interconnection network,this thesis focus on optical network,including topology design,rout-ing and resource reservation protocol,contention control,and so on.The main innovations are summarized as follows.(1)The topology design of nesting ring Multi-chip optical network on chip.With increasing IP cores to be integrated on the chip,the scalability of on-chip system is limited by process yield and power density of single chip.A multi-chip system canovercome the area constraint of a single chip.In this thesis,we propose a multi-chip architecture called nesting ring ONoC(NRO),which is based on a novel topology nesting ring topology.NRO includes inter-chip network and intra-chip network.The cores on a chip are interconnected by a nesting ring that consists of a series of small rings,and different chips are interconnected by single rings.Compared with traditional ring and CMesh topologies,the nesting ring topology reduce the core-to-core communication distance.To further improve the scalability of the NRO architecture and optimize the performance of ONoC with different numbers of cores,we propose a topology optimization scheme for each NRO with a given number of cores.Moreover,For a large-scale optical network on chip(in order of 1000 cores),theNRO architecture should be further optimized to guarantee a good network performance and maintain the power efficiency of the whole network as well.(2)Control strategy in large-scale network on chip.Control strategy plays an important role in an optical network on chip,es-pecially in a large-scale network on chip,because it influences the performance of network on throughput and delay.We compare the effect of forward resource reservation and backward resource reservation on optical network on chip,and simulation results show that backward resource reservation can decrease the contentions for resource during the path-setup process.On this basis,we pro-pose an novel resources planning scheme that offers more wavelengths for key nodes,and design corresponding switching structure to reduce the contention caused by the shortage of optical resource.At the same time,the ordinary nodes keep the original resource in this scheme to guarantee good power efficiency.In addition,to mitigate the impact of the inevitable contentions,we also propose a k-path routing contention management scheme,which buffers the blocked mes-sage or re-routes it depending on the location of the contention.The proposed scheme can reduce the effect of contentions on the performance.(3)Application-based dynamically reconfigurable optical network on chip architecture.Real-world application for chip multiple processors presents time-varying in traffic patterns.However,most of optical network on chip architectures are designed for one or several traffic patterns.These architecture may perform good under some traffic patterns but perform poorly under other traffic patterns.Reconfigurable optical network on chip architecture can dynamically reconfig-ure the network topology based on communication requirement of real-time traffic.In this thesis,we propose a reconfigurable ONoC architecture called TFONoC,which can be reconfigured neither Torus or Firefly network to route various traffic.To implement the reconfiguration,we propose a compound re-configurable optical router(OR)structure,which has low power consumption.We also propose an effective and low-cost reconfiguration algorithm,which determines whether to reconfigure the network depending on real-time traffic pattern to optimize overall performance of network.
Keywords/Search Tags:chip multiprocessor, optical network on chip, reconfig-urable optical network on chip, multi-chip architecture, routing and resource algorithm, contention control
PDF Full Text Request
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