| The rapid rise of emerging fields such as 5G communication,big data,and artificial intelligence has led to the development of memory chips towards miniaturization and high integration.At the same time,higher requirements have been put forward for the packaging methods of memory chips.At present,memory chips are packaged by three-dimensional stacking packaging,which has the advantages of large storage capacity and high integration.However,with the increasing frequency and power of memory chips,three-dimensional stacked packaging is difficult to meet the heat dissipation requirements of the chip,which is easy to cause chip warpage,cracking,and even interface delamination and other failure problems,seriously affecting the performance and service life of memory chips.Therefore,improving the service reliability of 3D stacked packaging technology has become an important means to solve the failure of memory chips.The paper takes a typical six-layer stacked package memory chip as the research object,uses the finite element simulation and experimental characterization to study the thermal force and interface reliability of the device during service,and proposes an optimization scheme.The specific research contents are as follows:(1)Based on the simulation analysis,the thermal characteristics of the memory chip stack package module are analyzed.Referring to the existing memory chip information,a six-layer memory chip stack package model is established to explore the influence of each component material on the chip junction temperature.The results show that a certain degree of thermal coupling phenomenon occurs because each layer of chips in the module is an independent heat source.The temperature at the overlap of each layer of chips is relatively high,and the thickness of the adhesive is the principal element.And to confirm the main heat dissipation path of the package module,that is,the heat generated by the memory chip is transferred to the PCB through the substrate and then dissipated to the surrounding environment.(2)Based on simulation and experimental characterization,the mechanical properties of stacked packaging modules of memory chips were analyzed.The dynamic mechanical analyzer and thermomechanical analyzer were used to carry out mechanical property characterization experiments,and Young’s modulus,glass transition temperature,and thermal expansion coefficient of the molding compound were obtained.Apply temperature cycle loads to the model through simulation,observe the thermal stress and strain changes under high and low temperature conditions,and explore the influence of each component material on the maximum equivalent stress of the packaging module,laying the foundation for subsequent packaging structure optimization.The results show that the maximum equivalent stress appears at the corner of the interface between the bottom chip,the molding compound,and the adhesive layer.The thickness of the molding compound is the principal element.In addition,the dual-objective optimization design of the thermal and mechanical performance of the packaging module is carried out by using the orthogonal test and the gray relational analysis method.(3)Based on the optimized combination of the packaging structure obtained above,the simulation analysis and the lamination test stretching method are used to analyze the lamination problem of the interface between the plastic encapsulant and the chip,and a set of cohesion parameters of the interface are obtained.Based on the existing instrument fixture,an experimental loading device combining a loading block and a restraining guide plate is designed.Tensile experiments were carried out on the prepared samples using a thermomechanical analyzer,and the force-displacement curves that caused the interface delamination between the molding compound and the chip were obtained.Finally,the critical energy release rate is calculated,and the ultimate tensile strength is obtained based on the simulation analysis.The simulation results are consistent with the experimental results.In conclusion,the article preliminarily explores the thermal,mechanical,and interface reliability issues of memory chip stacked package modules,providing a certain reference and guiding value for actual production and application to some extent. |
