Stress Finite Element Analysis And Structure Optimization In A Stacked Chip Size Package

In this thesis, packaging process for a typical four-chip CSP(chip size package) product, FTA073, is studied in detail. FEA(Finite element analysis) has been applied in three major process steps which cover temperature change, including (1) the 1st die attach cure, (2) the 2nd, 3rd and 4th die attach cure and (3) postmold cure for packaging failures in die crack, delamination and warpage. By comparing the influence of process including temperature change on packaging reliability in this stacked CSP packaging process, it is found that the second, third and fourth die attach cure process will bring more destructivity than other two steps. In consideration of distribution stress that the different unit locations bring in the block model, the FEA simulation results of unit model are compared with that of block model. It is found that the FEA simulation results of unit model will have a certain deviation if the distribution stress is neglected. But this deviation has no obvious effect on the results.For certain product packaging process the variation of product component thicknesses will bring changes of the stress distribution on the die and die attach. So for a typical CSP product FEA and design of experiments are adopted to systematically investigate the influence of component thicknesses on maximum thermal stress of die and die attach which postmold cure process brings. These components include all layers involved in CSP structure such as dies, die attaches, mould compound, and top die passivation. It is found that in current packaging process top die of CSP is more prone to crack under thermal stress than other dies. The maximum tensile stress in top die depends essentially on top die thickness and corresponding die attach thickness. When these two factors are optimized to an appropriate value, the maximum stress of top die can be effectively lowered. The maximum shear stress of die attach is only sensitive to thickness itself, and the warpage of product is only sensitive to molding compound thickness. These impact factors investigated have been utilized to optimize this CSP structure. Structure optimization of the package design in different approaches shows that thinner package body, lower chip stress level and smaller package warpage can be realized in this product. Our study would be beneficial to improve the reliability of stacked CSP products.