A Study On Thermal Stress And Invalidation For Chip Scale Package

The new generation computers and electronic devices are characterized with minimized package profile and maximum interconnect density. Be praised as the new generation package-chip scale package, with small pitch and little volume, but also exists some problems. The test study on chip scale package is little, also in a computer simulative analysis phase.The paper firstly summarizes the different types and normal invalidation of chip scale package. Hereby, the paper selects a special CSP product-chip scale package-substrate on chip, using the ANSYS builds the two dimension 1/2 model of cross section and three dimension 1/4 model of whole package, then on the condition of the standard industry thermal cycle temperature-40℃～125℃, combining APDL command language, completing the control of thermal cycle temperature load, simulating the thermal stress and strain of CSP-SOC under the above-mentioned condition. Then completed the parameters analysis from the materials and design, and compared the two dimension and three dimension analysis results, then compare with the precedent test result, analysize the invalidation and life prediction, bring forward a new formula on life prediction, establish a good base for the high density package in future.The results show that the package, due to different coefficient of thermal expanded(CTE), engenders thermal stress and strain, it will make the package disabled when theintension is low than thermal stress. And the maximum deformed displacement of the wholepackage occurs in PCB. To solder balls, the maximum stress and strain occurs in the outersolder ball. To the three dimension model, additional direction is considered, it is found thatthe maximum elastic strain exists in the interface of the solder balls and PCB, and theminimum strain exsits in the underfill tape, the whole package stress occurs in the edge areaof chip, it is also proved that the solder balls are placed around the chip better than under thechip, it is more reasonable and advanced. Comparing the stress and strain distribution resultswith the similar package test results, it is consistent. For all, the stress and strain isn't reflectedin the 2D model, but from the figure of the deformed displacement opposite to time, we cansee that the maximum displacement on solder joint is increasing along X direction nolinearly,and is fluctuant along Y direction due to suffering from temperature impact but is invariably after three cycle of temperature. The stress variation is bigger along with time in the temperature cycling moment, but it is balanced subsequently. This may say the PCB provides a good sustentation for the solder joint and substrate when is normally Woking.In virtue of the energy-based fatigue model and a simplified model to calculate the life of solder joint and the whole package respectively. Comparing the result, former model calculating process is complicated, and the two results are consistent. A new simple model is mended and gained, comparing the previous similar test life with the calculated life; the error is 10% only lower than standard deviation.