Research And Design Of Reconfigurable Array Processor For Communication Baseband Signal Processing

Reconfigurable architecture has great potential in computing intensive and memory intensive applications due to its flexible information configuration.The emergence of new applications in mobile communication technology has put forward higher requirements on the hardware performance of communication baseband signal processing.The reconfigurable architecture,which has advantages in the field of parallel computing,has become an ideal hardware platform to implement baseband signal processing algorithm.However,the implementation of baseband signal processing algorithm on reconfigurable array processor has problems of poor adaptability and low computational efficiency.Therefore,this thesis studies and designs a reconfigurable array processor for baseband signal processing.Firstly,the operators of typical algorithms for communication baseband signal processing are extracted,and the fixed-point accuracy of the algorithms is evaluated to guide the design of reconfigurable array processor.On the one hand,the characteristics of Fast Fourier Transform(FFT),Finite Impulse Response(FIR)and massive Multiple-Input Multiple-Output(MIMO)detection algorithms are obtained by Profile performance analysis tool,and abstract coarse-grained operators are extracted.On the other hand,the experimental results of fixed-point simulation show that the fixed-point precision curve can converge when the hardware structure has more than 15 bits data width.Secondly,aiming at the poor adaptability of baseband signal processing algorithm on reconfigurable array processor,a reconfigurable process element for communication applications is designed.The Process Element(PE)expands the 16-bit data width to 32-bit to accommodate complex operations.At the same time,special instructions for baseband signal processing are added to the PE.The experimental results of complex matrix multiplication performed by the reconfigurable process element show that the implementation method of the special instruction shortens 74%of the code lines,reduces the number of memory access by 61%,and reduces the average relative error by 85%compared with the general instruction.Thirdly,aiming at the problem of low computing efficiency caused by disharmony between the data of different granularity and the underlying hardware structure,a structure of computational granularity dynamic configuration is proposed.The structure divides the computing granularity into 8-bit,16-bit and 32-bit,and designs four functions of data combination,data splitting,parallel addition and parallel multiplication,which improves the parallelism and flexibility of the array structure.The experimental results show that the maximum working frequency of the dynamic configuration circuit is 133.5MHz,which can realize the dynamic configuration of different granularity data in the calculation.Finally,a reconfigurable array prototype system for communication baseband signal processing is developed,and a reconfigurable implementation scheme for FFT algorithm,FIR algorithm and massive MIMO detection algorithm is designed,and Field Programmable Gate Array(FPGA)verification is completed.The reconfigurable implementation results show that the parallelization scheme of butterfly operation module provides 2.90 times speedup for 8-point FFT algorithm,the pipeline-parallel scheme of filtering calculation provides 7.28 times speedup for 8-order FIR filter algorithm,and Gram matrix computation parallelization scheme provides a maximum speedup of 5.57 times for massive MIMO detection algorithm.The hardware experiment results based on ZC706 development board show that the resource utilization rate of the reconfigurable array processor is less than 60%at the frequency of 112MHz,which achieves flexible configuration and parallel acceleration of different algorithms on the array structure.