Investigation On Optimization Algorithm Of Complementary Use Of Different Registers Of Symbol Register Spilling For Vector DSP Processor

Modern DSP processors have very good performance,especially vector DSP processors having both scalar and vector processing units.Registers,as a limited valuable hardware resource in processor,make register allocation one of the most critical processes in the compiler.When the number of registers is limited and the actual physical registers cannot be completely allocated to those register allocation candidates,the general method is to temporarily store the data in the memory.This will increase the access to memory,reduce the execution efficiency of codes and also bring about additional energy consumption.Therefore,one of the key factors influencing the effect of the register allocation is to reduce the access to memory due to overflow.Modern high-performance vector DSP processors often have multiple types of register resources.Therefore,it is an important optimization method to cache the data of a certain type of symbol registers to reduce the additional access to memory caused by register overflow by the complementary optimizing use between different classes registers.This paper analyzes these unfavorable factors and conducts an spilling optimization study taking the web as the register allocation candidate based on the global graph coloring register allocation combing the characteristics of vector DSP processors.The optimization study includes the following aspects:1.Complementary optimizing use between different classes registers in the same processing unit.When register spilling occurs,the algorithm examine whether it is possible to spill the web to one of the other types of registers that are free or free in a certain time slice.Traversing and recognizing all the webs in scalar and vector processing unit,then optimization is executed in different processing unit.Determining the spilling web's last overflow space,then the loading and restoring instructions are inserted to original code based on traditional algorithm to optimize the spilling web.In general,optimizing use between different classes registers can significantly save the time cost of code execution compared to overflowing the web into memory.2.Using the SVR registers to cache spilling data in scalar processing unit.SVR registers are channel registers between scalar processing unit and vector processing unit.Assuming that the vector unit and scalar unit do not use the SVR register at the same time,only the scalar unit may occupy the SVR register here.An overflow of the scalar web is occurring when the general-purpose register is not enough,then find if there is an idle SVR register in the web lifetime to cache the current data.Multiple webs may overflow to the same SVR register as long as the life span of these webs is not interlaced.Using the channel register reasonably as an overflow buffer not only can accelerate the execution speed of the code and improves the utilization of hardware resources,but also reduce the memory access pressure of the processing unit by caching the web to the SVR register.3.Using the SVR registers to cache spilling data in vector processing unit.Assuming that the vector unit and scalar unit do not use the SVR register at the same time,only the vector unit may occupy the SVR register here.Although there is only one SVR register for the vector unit,as long as this register is free during the overflow net lifetime,the spilling web can still be buffered into this channel register.There also is possibility that multiple webs may overflow to the same SVR register as long as the life span of these webs is not interlaced.Optimizing the spilling webs in vector processing unit by caching data to SVR register not only can improve the utilization of registers but also significantly save a lot of storage space.