Research On Polar Code Decoding Algorithms And Implementation Of Decoder

In wireless communication systems,channel coding and decoding techniques are employed to ensure distortion-free information exchange through the channel and improve the system’s resistance to interference.In 2009,researcher Erdal Arikan proposed polar coding,which was the first coding scheme rigorously proven to achieve the Shannon limit.This coding scheme was subsequently adopted as the coding scheme for control channels in the enhanced mobile broadband scenario of 5G in 2016.Polar codes have gained widespread application in digital communication systems due to their low encoding and decoding complexity and the ability to utilize parallel decoding architectures.In this paper,we provide a detailed discussion and introduction to the theory of polar code encoding and decoding.We elaborate on the significance of channel polarization phenomenon in polar code encoding and explain the process of obtaining polarized subchannels through channel combining and channel splitting.Additionally,we describe the encoding process of polar codes and methods for estimating channel reliability.Building upon this foundation,we introduce and analyze the decoding algorithms for polar codes.The thesis begins by analyzing and discussing the successive cancellation algorithm in both the binary field and the real field,and provide a detailed description of the construction of the decoding tree.However,due to the subpar decoding performance of the successive cancellation algorithm for medium to short code lengths,we further discuss the successive cancellation list algorithm and illustrate the decoding process with examples.Furthermore,the thesis performs performance simulations and analyze the results for the successive cancellation list algorithm incorporating cyclic redundancy check.The simulation results demonstrate that the decoding performance of the algorithm improves as more decoding paths are retained,but the decoding time complexity also increases significantly.As the number of retained paths in the decoding algorithm increases,the delay and resource consumption of the successive cancellation list decoder also increase.Therefore,we simplify the problem to the issue of data output in sorted order.Firstly,we design a parallel sorting network based on the principles of bubble sort,which reduces the time complexity to some extent through pipeline design.However,this sorting network has high hardware resource requirements and is suitable for limited scenarios.To further reduce the delay and resource consumption in the decoding path selection process,we propose a logic-based comparison sorting network.Its basic principle involves using binary logic comparators to solve the data comparison problem.The thesis then analyzes the algorithm and provide a detailed description of the hardware implementation of the logic-based comparison sorter,including the working principles and architecture of each module.Compared to traditional comparison-exchange-based networks,this sorting network has the advantage of requiring a fixed cycle to complete data sorting.Finally,we combine the logic-based comparison sorting network with path metric properties and propose a metric-based path selector using the logic-based comparison sorting network.Its prominent advantage lies in its fixed cycle and reduced resource usage.We validate and analyze the functionality and timing of these proposed solutions using a hardware simulation platform.The results show that the metric-based path selector can consume fewer hardware resources and achieve path selection within a fixed cycle.Lastly,we present the overall hardware architecture implementation of the successive cancellation list algorithm.We first explore two decoder implementation architectures that facilitate hardware operation.Then,addressing the issue of high resource consumption when handling floating-point data in hardware,we propose a fixed-point quantization scheme that not only controls resource consumption but also limits the range and precision of decoded information.Then,it describes in detail the FPGA implementation of the decoder,systematically introduces the design ideas of each internal module,and verifies the functionality of each module.Finally,the thesis writes the modules in Verilog HDL language in the EDA tool Quartus II and conducts RTL-level verification simulation using Modelsim,completing the design.