Design And Application Of Approximate Multipliers Based On Truncation And Error Compensation

With the rapid development of technologies such as autonomous driving,cloud computing,and multimodal large models,the hardware design of high-performance computing has become more and more important,in which the computing unit consumes large amount of power.Since multipliers typically lie in the bottleneck of computational circuits,design of energy-efficient multiplier circuit attracts the attention of research in recent years.While fortunately,high-precision is not always compulsory for computations such as artificial intelligence.Therefore,approximation computing becomes a popular design approach for those error-tolerant applications in the design of multipliers.Moreover,truncation and error compensation is one of the most efficient approximation design methods of multipliers.In this thesis,we first propose an approximation scheme and an error model for approximate Booth multipliers based on truncation and compensation.In the design scheme,Booth encoder using static segment method are proposed,detecting whether the high significant segments are redundant and generating patial product array according to the detecting result.The design of partial product compression circuit is based on partial product array truncation and compensation.The error compensation model of the compensation circuit is given to determine the truncation and compensation scheme of the partial product compression circuit.Based on the proposed error model of truncation compensation,various novel 8-bit and 16-bit approximate multipliers with different truncation and compensation schemes are proposed in this thesis according to the number of retained partial product rows and truncated partial product columns.With proposed static segmentation method of operands and truncation and compensation method of the partial product array,proposed designs have greater gains in hardware performance indexes compared with the exact multiplier while the accuracy is effectively controlled.Compared with other designs,proposed multipliers achieve the optimal hardware performance index at the same accuracy level.The evaluation results show that proposed approximate multipliers achieve excellent accuracy and hardware performance tradeoffs for different bit widths and different patterns of input operands.Proposed approximate multipliers are applied to the hardware implementation of image edge detection and FIR digital filter design.Then,the accuracy and hardware performance metrics are evaluated to show the applicability of proposed designs.From the evaluation results of applications,it is concluded that proposed multipliers are suitable for different hardware systems of image processing and digital signal processing.